| Unification of multimedia devices S Bryce, T Celinski, AJ Kent US Patent 7,987,294, 2011 | 1256 | 2011 |
| Consolidated data services apparatus and method TJ Caplis, VO Giuliani, ACL Brogestam, P Celinski US Patent 8,572,685, 2013 | 170 | 2013 |
| Media data synchronization in a wireless network T Celinski, P Celinski, S Bryce, MG Ramsay, AJ Kent, A Kaczynski US Patent 7,539,889, 2009 | 137 | 2009 |
| Low power, high speed, charge recycling CMOS threshold logic gate P Celinski, JF López, S Al-Sarawi, D Abbott Electronics Letters 37 (17), 1, 2001 | 66 | 2001 |
| State of the art in CMOS threshold logic VLSI gateimplementations and applications P Celinski, SD Cotofana, JF Lopez, SF Al-Sarawi, D Abbott VLSI Circuits and Systems 5117, 53-64, 2003 | 31 | 2003 |
| Compact parallel (m, n) counters based on self-timed threshold logic P Celinski, JF López, S Al-Sarawi, D Abbott Electronics Letters 38 (13), 633-635, 2002 | 20 | 2002 |
| Delay analysis of neuron-MOS and capacitive threshold-logic P Celinski, S Al-Sarawi, D Abbott ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000 | 19 | 2000 |
| Low depth, low power carry lookahead adders using threshold logic P Celinski, JF López, S Al-Sarawi, D Abbott Microelectronics journal 33 (12), 1071-1077, 2002 | 14 | 2002 |
| Low depth carry lookahead addition using charge recycling threshold logic P Celinski, S Al-Sarawi, D Abbott, JF López 2002 IEEE International Symposium on Circuits and Systems (ISCAS) 1, I-I, 2002 | 11 | 2002 |
| Logical effort based design exploration of 64-bit adders using a mixed dynamic-cmos/threshold-logic approach P Celinski, S Al-Sarawi, D Abbott, S Cotofana, S Vassiliadis IEEE Computer Society Annual Symposium on VLSI, 127-132, 2004 | 10 | 2004 |
| Media data transfer in a network environment T Celinski, P Celinski, S Bryce, MG Ramsay US Patent 8,462,627, 2013 | 8 | 2013 |
| System and method for controlling a rendering device based upon detected user proximity N Murrells, P Celinski, MR Wachter, A Brogestam US Patent 9,825,969, 2017 | 7 | 2017 |
| Area efficient, high speed parallel counter circuits using charge recycling threshold logic P Celinski, D Abbott, SD Cotofana Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003 | 6 | 2003 |
| Technique for implementing arbitrary Boolean functions in threshold logic P Celinski, GD Sherman, D Abbott Smart Electronics and MEMS II 4236, 339-350, 2001 | 5 | 2001 |
| Optical threshold logic analog-to-digital converters using self electro-optic effect devices T Sarros, SF Al-Sarawi, P Celinski, KA Corbett Smart Structures, Devices, and Systems II 5649, 227-236, 2005 | 4 | 2005 |
| A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions P Celinski, GD Sherman, JF Lopez, D Abbott Advances in Neural Networks and Applications 4236, 224-228, 2001 | 4 | 2001 |
| A-DELTA: A 64-bit high speed, compact, hybrid dynamic-CMOS/Threshold-Logic adder P Celinski, SD Cotofana, D Abbott International Work-Conference on Artificial Neural Networks, 73-80, 2003 | 3 | 2003 |
| Threshold logic parallel counters for 32-bit multipliers P Celinski, SD Cotofana, D Abbott Smart Structures, Devices, and Systems 4935, 205-214, 2002 | 3 | 2002 |
| Complementary neu-GaAs structure P Celinski, JF Lopez, S Al-Sarawi, D Abbott Electronics Letters 36 (5), 424-425, 2000 | 3 | 2000 |
| System and method for determining proximity of a controller to a media rendering device N Murrells, B Stead, P Celinski, A Brogestam US Patent 9,654,891, 2017 | 2 | 2017 |
