| Inside NAND flash memories R Micheloni, L Crippa, A Marelli Springer Science & Business Media, 2010 | 322 | 2010 |
| VLSI-design of non-volatile memories G Campardo, R Micheloni, D Novosel Springer, 2005 | 243 | 2005 |
| Inside solid state drives (SSDs) R Micheloni Springer, 2013 | 164 | 2013 |
| Error correction codes for non-volatile memories R Micheloni, A Marelli, R Ravasio Springer Science & Business Media, 2008 | 150 | 2008 |
| Memory with embedded error correction codes R Micheloni, R Ravasio, A Bovino, V Altieri US Patent 7,581,153, 2009 | 131 | 2009 |
| Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories O Khouri, R Micheloni, I Motta, A Sacco, G Torelli US Patent 6,259,635, 2001 | 127 | 2001 |
| Array architectures for 3-D NAND flash memories R Micheloni, S Aritome, L Crippa Proceedings of the IEEE 105 (9), 1634-1649, 2017 | 105 | 2017 |
| 3D Flash memories R Micheloni Springer Netherlands, 2016 | 101 | 2016 |
| Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude S Gregori, R Micheloni, A Pierin, O Khouri, G Torelli US Patent 6,788,579, 2004 | 100 | 2004 |
| A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36MB/s system read throughput R Micheloni, R Ravasio, A Marelli, E Alice, V Altieri, A Bovino, L Crippa, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 97 | 2006 |
| Nonvolatile memory controller with error detection for concatenated error correction codes R Micheloni, A Marelli, PZ Onufryk, CIW Norrie US Patent 8,621,318, 2013 | 86 | 2013 |
| Method for storing and reading data in a multilevel nonvolatile memory R Micheloni, G Campardo US Patent 6,646,913, 2003 | 78 | 2003 |
| Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories O Khouri, R Micheloni, I Motta, A Sacco, G Torelli US Patent 6,259,632, 2001 | 76 | 2001 |
| Architectural and integration options for 3D NAND flash memories R Micheloni, L Crippa, C Zambelli, P Olivo Computers 6 (3), 27, 2017 | 74 | 2017 |
| System and method with reference voltage partitioning for low density parity check decoding R Micheloni, A Marelli, PZ Onufryk US Patent 9,235,467, 2016 | 74 | 2016 |
| Circuit and method for generating a read reference signal for nonvolatile memory cells G Campardo, R Micheloni, M Maccarrone US Patent 5,805,500, 1998 | 74 | 1998 |
| 40-mm/sup 2/3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory G Campardo, R Micheloni, S Commodaro, E Yero, M Zammattio, ... IEEE Journal of Solid-State Circuits 35 (11), 1655-1667, 2000 | 70 | 2000 |
| Double page programming system and method R Micheloni, L Crippa, R Ravasio US Patent 7,366,014, 2008 | 57 | 2008 |
| The flash memory read path: building blocks and critical aspects R Micheloni, L Crippa, M Sangalli, G Campardo Proceedings of the IEEE 91 (4), 537-553, 2003 | 57 | 2003 |
| Nonvolatile memory controller with concatenated error correction codes R Micheloni, A Marelli, PZ Onufryk, CIW Norrie US Patent 8,656,257, 2014 | 55 | 2014 |
Cristian ZambelliAssociate Professor, University of FerraraVerified email at unife.it
