| Nonvolatile memory device and related programming method KT Park, MG Kang US Patent 8,300,463, 2012 | 394 | 2012 |
| Three-dimensional shared memory fabricated using wafer stacking technology KW Lee, T Nakamura, T Ono, Y Yamada, T Mizukusa, H Hashimoto, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 382 | 2000 |
| Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming KT Park, S Nam, D Kim, P Kwak, D Lee, YH Choi, MH Choi, DH Kwak, ... IEEE Journal of Solid-State Circuits 50 (1), 204-213, 2014 | 325 | 2014 |
| Method for operating non-volatile memory device and memory controller J Jeong, MH Choi, P Kitae US Patent 9,117,536, 2015 | 270 | 2015 |
| Semiconductor memory device with three-dimensional array and repair method thereof D Kim, K Park US Patent 8,031,544, 2011 | 244 | 2011 |
| A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories KT Park, M Kang, D Kim, SW Hwang, BY Choi, YT Lee, C Kim, K Kim IEEE Journal of Solid-State Circuits 43 (4), 919-928, 2008 | 213 | 2008 |
| A 512-Gb 3-b/cell 64-stacked WL 3-D-NAND flash memory C Kim, DH Kim, W Jeong, HJ Kim, IH Park, HW Park, JH Lee, JY Park, ... IEEE Journal of Solid-State Circuits 53 (1), 124-133, 2017 | 189 | 2017 |
| Intelligent image sensor chip with three dimensional structure H Kurino, KW Lee, T Nakamura, K Sakuma, KT Park, N Miyakawa, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 179 | 1999 |
| 256 Gb 3 b/cell V-NAND flash memory with 48 stacked WL layers D Kang, W Jeong, C Kim, DH Kim, YS Cho, KT Kang, J Ryu, KM Kang, ... IEEE Journal of Solid-State Circuits 52 (1), 210-217, 2016 | 177 | 2016 |
| Neuromorphic vision chip fabricated using three-dimensional integration technology M Koyanagi, Y Nakagawa, KW Lee, T Nakamura, Y Yamada, K Inamura, ... 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 168 | 2001 |
| NAND flash memory device having dummy memory cells and methods of operating same K Park, JD Choi, JS Sel, YC Shin US Patent 7,480,178, 2009 | 142 | 2009 |
| Future of active catheters G Lim, K Park, M Sugihara, K Minami, M Esashi Sensors and Actuators A: Physical 56 (1-2), 113-121, 1996 | 136 | 1996 |
| 7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate JW Im, WP Jeong, DH Kim, SW Nam, DK Shim, MH Choi, HJ Yoon, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 121 | 2015 |
| Negative voltage generator, decoder, nonvolatile memory device and memory system using negative voltage M Kim, J Im, JD Yu, P Kitae, O Kwon US Patent 8,705,273, 2014 | 117 | 2014 |
| A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput S Lee, C Kim, M Kim, S Joe, J Jang, S Kim, K Lee, J Kim, J Park, HJ Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 340-342, 2018 | 106 | 2018 |
| Read compensation circuits and apparatus using same KT Park US Patent 8,243,515, 2012 | 104 | 2012 |
| A multilink active catheter with polyimide-based integrated CMOS interface circuits KT Park, M Esashi Journal of microelectromechanical systems 8 (4), 349-357, 1999 | 99 | 1999 |
| Data storage system having multi-bit memory device and operating method thereof S Yoon, P Kitae, J Han, W Lee US Patent 8,355,280, 2013 | 90 | 2013 |
| Nonvolatile memory device and programming method S Hwang, P Kitae, J Lee, HS Joo US Patent 8,254,181, 2012 | 89 | 2012 |
| Memory array architecture for a memory device and method of operating the memory array architecture K Park, JD Choi US Patent 7,408,806, 2008 | 87 | 2008 |
