| 5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor Z Toprak-Deniz, M Sperling, J Bulzacchelli, G Still, R Kruse, S Kim, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 143 | 2014 |
| Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage JF Bulzacchelli, Z Toprak-Deniz, TM Rasmus, JA Iadanza, WL Bucossi, ... IEEE Journal of Solid-State Circuits 47 (4), 863-874, 2012 | 131 | 2012 |
| 5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth EJ Fluhr, J Friedrich, D Dreps, V Zyuban, G Still, C Gonzalez, A Hall, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 120 | 2014 |
| Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications A Rylyakov, J Tierno, H Ainspan, JO Plouchart, J Bulzacchelli, ZT Deniz, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 90 | 2009 |
| A 32 Gb/s, 4.7 pJ/bit optical link with− 11.7 dBm sensitivity in 14-nm FinFET CMOS JE Proesel, Z Toprak-Deniz, A Cevrero, I Ozkaya, S Kim, DM Kuchta, ... IEEE Journal of Solid-State Circuits 53 (4), 1214-1226, 2017 | 67 | 2017 |
| A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS H Chung, A Rylyakov, ZT Deniz, J Bulzacchelli, GY Wei, D Friedman 2009 Symposium on VLSI Circuits, 268-269, 2009 | 67 | 2009 |
| The 12-core power8™ processor with 7.6 tb/s io bandwidth, integrated voltage regulation, and resonant clocking EJ Fluhr, S Baumgartner, D Boerstler, JF Bulzacchelli, T Diemoz, D Dreps, ... IEEE Journal of Solid-State Circuits 50 (1), 10-23, 2014 | 60 | 2014 |
| A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS Z Toprak-Deniz, JE Proesel, JF Bulzacchelli, HA Ainspan, TO Dickson, ... IEEE Journal of Solid-State Circuits 55 (1), 19-26, 2019 | 58 | 2019 |
| Dual-loop voltage regulator architecture with high DC accuracy and fast response time JF Bulzacchelli, CE Cox, Z Toprak-Deniz, DJ Friedman, JA Iadanza, ... US Patent 8,841,893, 2014 | 46 | 2014 |
| A 78mW 11.1 Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS JF Bulzacchelli, TO Dickson, ZT Deniz, HA Ainspan, BD Parker, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 45 | 2009 |
| A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration TO Dickson, Y Liu, A Agrawal, JF Bulzacchelli, HA Ainspan, ... IEEE Journal of Solid-State Circuits 51 (8), 1744-1755, 2016 | 41 | 2016 |
| 3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI S Rylov, T Beukema, Z Toprak-Deniz, T Toifl, Y Liu, A Agrawal, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 56-57, 2016 | 32 | 2016 |
| Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control HA Ainspan, JF Bulzacchelli, ZT Deniz, DJ Friedman, AV Rylyakov, ... US Patent 8,138,840, 2012 | 31 | 2012 |
| Technique for linearizing the voltage-to-frequency response of a VCO JF Bulzacchelli, ZT Deniz, DJ Friedman, S Naraghi, AV Rylyakov US Patent 8,294,525, 2012 | 29 | 2012 |
| The POWER8TM processor: Designed for big data, analytics, and cloud environments J Friedrich, H Le, W Starke, J Stuechli, B Sinharoy, EJ Fluhr, D Dreps, ... 2014 IEEE International Conference on IC Design & Technology, 1-4, 2014 | 24 | 2014 |
| IBM POWER8 circuit design and energy optimization V Zyuban, J Friedrich, DM Dreps, J Pille, DW Plass, PJ Restle, ZT Deniz, ... IBM Journal of Research and Development 59 (1), 9: 1-9: 16, 2015 | 23 | 2015 |
| Distributed network of LDO microregulators providing submicrosecond DVFS and IR drop compensation for a 24-core microprocessor in 14-nm SOI CMOS ME Perez, MA Sperling, JF Bulzacchelli, Z Toprak-Deniz, TE Diemoz IEEE Journal of Solid-State Circuits 55 (3), 731-743, 2019 | 18 | 2019 |
| Time-to-digital based analog-to-digital converter architecture JF Bulzacchelli, DJ Friedman, S Naraghi, SV Rylov, AV Rylyakov, ... US Patent 7,893,861, 2011 | 17 | 2011 |
| Analog to digital converter with high precision offset calibrated integrating comparators T Beukema, Y Liu, S Rylov, MA Sanduleanu, ZT Deniz US Patent 9,571,115, 2017 | 16 | 2017 |
| Track and hold amplifiers and digital calibration for analog-to-digital converters MAT Sanduleanu, JO Plouchart, ZT Deniz US Patent 8,350,738, 2013 | 14 | 2013 |
