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Chetan Prasad
Chetan Prasad
Verified email at intel.com
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A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging
K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ...
2007 IEEE International Electron Devices Meeting, 247-250, 2007
16942007
BTI reliability of 45 nm high-K+ metal-gate process technology
S Pae, M Agostinelli, M Brazier, R Chau, G Dewey, T Ghani, M Hattendorf, ...
2008 IEEE International Reliability Physics Symposium, 352-357, 2008
1552008
45nm Transistor Reliability.
J Hicks, D Bergstrom, M Hattendorf, J Jopling, J Maiz, S Pae, C Prasad, ...
Intel Technology Journal 12 (2), 2008
1222008
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
C Prasad, L Jiang, D Singh, M Agostinelli, C Auth, P Bai, T Eiles, J Hicks, ...
2013 IEEE International Reliability Physics Symposium (IRPS), 5D. 1.1-5D. 1.5, 2013
1172013
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for …
CH Jan, F Al-Amoody, HY Chang, T Chang, YW Chen, N Dias, W Hafez, ...
2015 Symposium on VLSI Technology (VLSI Technology), T12-T13, 2015
1032015
Effect of BTI degradation on transistor variability in advanced semiconductor technologies
S Pae, J Maiz, C Prasad, B Woolery
IEEE Transactions on Device and Materials Reliability 8 (3), 519-525, 2008
962008
Method to fabricate high-k/metal gate transistors using a double capping layer process
S Pae, J Maiz, C Prasad
US Patent App. 11/527,263, 2008
942008
Self-heating in advanced CMOS technologies
C Prasad, S Ramey, L Jiang
2017 IEEE International Reliability Physics Symposium (IRPS), 6A-4.1-6A-4.7, 2017
582017
Frequency and recovery effects in high-κ BTI degradation
S Ramey, C Prasad, M Agostinelli, S Pae, S Walstra, S Gupta, J Hicks
2009 IEEE International Reliability Physics Symposium, 1023-1027, 2009
572009
A review of self-heating effects in advanced CMOS technologies
C Prasad
IEEE Transactions on Electron Devices 66 (11), 4546-4555, 2019
552019
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
CH Jan, P Bai, S Biswas, M Buehler, ZP Chen, G Curello, S Gannavaram, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
542008
Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures
C Prasad, M Agostinelli, J Hicks, S Ramey, C Auth, K Mistry, S Natarajan, ...
2014 IEEE International Reliability Physics Symposium, 6A. 5.1-6A. 5.7, 2014
522014
Random charge effects for PMOS NBTI in ultra-small gate area devices
M Agostinelli, S Pae, W Yang, C Prasad, D Kencke, S Ramey, E Snyder, ...
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005
482005
Transistor reliability variation correlation to threshold voltage
S Ramey, M Chahal, P Nayak, S Novak, C Prasad, J Hicks
2015 IEEE International Reliability Physics Symposium, 3B. 2.1-3B. 2.6, 2015
312015
Coupling-driven transition from multiple to single-dot interference in open quantum-dot arrays
M Elhassan, JP Bird, A Shailos, C Prasad, R Akis, DK Ferry, Y Takagaki, ...
Physical Review B 64 (8), 085325, 2001
292001
Magnetic-field-controlled electron dynamics in quantum cavities
Y Takagaki, M ElHassan, A Shailos, C Prasad, JP Bird, DK Ferry, ...
Physical Review B 62 (15), 10255, 2000
292000
Dielectric breakdown in a 45 nm high-k/metal gate process technology
C Prasad, M Agostinelli, C Auth, M Brazier, R Chau, G Dewey, T Ghani, ...
2008 IEEE International Reliability Physics Symposium, 667-668, 2008
282008
Phase breaking and energy relaxation in open quantum-dot arrays
C Prasad, DK Ferry, A Shailos, M Elhassan, JP Bird, LH Lin, N Aoki, ...
Physical Review B 62 (23), 15356, 2000
282000
Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms
C Prasad, KW Park, M Chahal, I Meric, SR Novak, S Ramey, P Bai, ...
2016 IEEE International Reliability Physics Symposium (IRPS), 4B-5-1-4B-5-8, 2016
272016
Aging model challenges in deeply scaled tri-gate technologies
S Ramey, Y Lu, I Meric, S Mudanai, S Novak, C Prasad, J Hicks
2015 IEEE International Integrated Reliability Workshop (IIRW), 56-62, 2015
252015
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