| Study of multilevel programming in programmable metallization cell (PMC) memory U Russo, D Kamalanathan, D Ielmini, AL Lacaita, MN Kozicki IEEE transactions on electron devices 56 (5), 1040-1047, 2009 | 377 | 2009 |
| Voltage-driven on–off transition and tradeoff with program and erase current in programmable metallization cell (PMC) memory D Kamalanathan, U Russo, D Ielmini, MN Kozicki IEEE Electron Device Letters 30 (5), 553-555, 2009 | 82 | 2009 |
| Conductive-bridge memory (CBRAM) with excellent high-temperature retention JR Jameson, P Blanchard, C Cheng, J Dinh, A Gallo, V Gopalakrishnan, ... 2013 IEEE International Electron Devices Meeting, 30.1. 1-30.1. 4, 2013 | 81 | 2013 |
| Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse D Kamalanathan, FS Koushan, JPS Echeverry, J Dinh, SC Hollmer, ... US Patent 9,165,644, 2015 | 47 | 2015 |
| Subquantum conductive-bridge memory JR Jameson, D Kamalanathan Applied Physics Letters 108 (5), 2016 | 40 | 2016 |
| ON state stability of programmable metalization cell (PMC) memory D Kamalanathan, S Baliga, SCP Thermadam, M Kozicki 2007 Non-Volatile Memory Technology Symposium, 91-96, 2007 | 26 | 2007 |
| Low voltage cycling of programmable metallization cell memory devices D Kamalanathan, A Akhavan, MN Kozicki Nanotechnology 22 (25), 254017, 2011 | 24 | 2011 |
| Conductive bridging RAM (CBRAM): then, now, and tomorrow JR Jameson, P Blanchard, J Dinh, N Gonzales, V Gopalakrishnan, ... ECS Transactions 75 (5), 41, 2016 | 23 | 2016 |
| An 8-bit 20.7 TOPS/W multi-level cell ReRAM-based compute engine JM Correll, L Jie, S Song, S Lee, J Zhu, W Tang, L Wormald, J Erhardt, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 22 | 2022 |
| Solid electrolyte memory for flexible electronics SR Baliga, SCP Thermadam, D Kamalanathan, DR Allee, MN Kozicki 2007 Non-Volatile Memory Technology Symposium, 86-90, 2007 | 11 | 2007 |
| Resistive switching memories JPS Echeverry, D Kamalanathan US Patent 9,029,829, 2015 | 9 | 2015 |
| Reverse program and erase cycling algorithms D Kim, D Kamalanathan, FS Koushan US Patent 8,995,167, 2015 | 8 | 2015 |
| Two terminal resistive access devices and methods of formation thereof D Kamalanathan, FS Koushan US Patent 9,373,786, 2016 | 7 | 2016 |
| Circuits and methods for placing programmable impedance memory elements in high impedance states D Kamalanathan, JPS Echeverry, VP Gopinath US Patent 8,730,752, 2014 | 7 | 2014 |
| Kinetics of Programmable Metallization Cell Memory D Kamalanathan Arizona State University, 2011 | 7 | 2011 |
| A Fully Integrated System‐on‐Chip Design with Scalable Resistive Random‐Access Memory Tile Design for Analog in‐Memory Computing F Cai, SH Yen, A Uppala, L Thomas, T Liu, P Fu, X Zhang, A Low, ... Advanced Intelligent Systems 4 (8), 2200014, 2022 | 6 | 2022 |
| An ultra low-power non-volatile memory design enabled by subquantum conductive-bridge RAM N Gonzales, J Dinh, D Lewis, N Gilbert, B Pedersen, D Kamalanathan, ... 2016 IEEE 8th International Memory Workshop (IMW), 1-4, 2016 | 5 | 2016 |
| Pre-conditioning circuits and methods for programmable impedance elements in memory devices FS Koushan, D Kamalanathan, JPS Echeverry, VP Gopinath, J Wang US Patent 9,025,396, 2015 | 5 | 2015 |
| Resistive switching memory with cell access by analog signal controlled transmission gate VP Gopinath, D Kamalanathan, D Wang US Patent 9,472,272, 2016 | 3 | 2016 |
| Safeguarding data through an SMT process J Dinh, D Lewis, VP Gopinath, D Kamalanathan, SC Hollmer, ... US Patent 9,007,808, 2015 | 3 | 2015 |
Michael KozickiArizona State UniversityVerified email at asu.edu
