Hira Taqdees Syeda
Hira Taqdees Syeda
Postdoctoral Researcher, Division of Formal Methods, CSE, Chalmers
Verified email at chalmers.se - Homepage
Title
Cited by
Cited by
Year
Formalization of laplace transform using the multivariable calculus theory of HOL-light
HT Syeda, O Hasan
International Conference on Logic for Programming Artificial Intelligenceá…, 2013
412013
Reasoning about Translation Lookaside Buffers
HT Syeda, G Klein
International Conference on Logic for Programming Artificial Intelligenceá…, 2017
122017
Program verification in the presence of cached address translation
HT Syeda, G Klein
International Conference on Interactive Theorem Proving, 542-559, 2018
112018
Formally Verifying Transfer Functions of Linear Analog Circuits
HT Syeda, O Hasan
IEEE Design & Test, 2017
7*2017
Do you have space for dessert? a verified space cost semantics for CakeML programs
A Gˇmez-Londo˝o, J ┼man Pohjola, HT Syeda, MO Myreen, YK Tan
Proceedings of the ACM on Programming Languages 4 (OOPSLA), 1-29, 2020
52020
Formal Reasoning Under Cached Address Translation
HT Syeda, G Klein
Journal of Automated Reasoning, 2020
42020
Formal verification of continuous models of analog circuits
HT Syeda, O Hasan
Frontiers in Analog CAD, Poster Paper, 2013
2*2013
Formally verifying transfer functions of analog circuits using theorem proving
HT Syeda, O Hasan
National University of Sciences and Technology, 2017
12017
Low-level program verification under cached address translation.
HT Syeda
University of New South Wales, Sydney, Australia, 2019
2019
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Articles 1–9