| Virtual machines: versatile platforms for systems and processes J Smith, R Nair Elsevier, 2005 | 1203 | 2005 |
| The architecture of virtual machines JE Smith, R Nair Computer 38 (5), 32-38, 2005 | 925 | 2005 |
| Efficient algorithms for testing semiconductor random-access memories R Nair, SM Thatte, JA Abraham IEEE Transactions on Computers, 572-576, 1978 | 256 | 1978 |
| Generation of performance constraints for layout R Nair, CL Berman, PS Hauge, EJ Yoffa IEEE transactions on computer-aided design of integrated circuits and …, 1989 | 238 | 1989 |
| Near-data processing: Insights from a MICRO-46 workshop R Balasubramonian, J Chang, T Manning, JH Moreno, R Murphy, R Nair, ... IEEE Micro 34 (4), 36-42, 2014 | 195 | 2014 |
| Dynamic path-based branch correlation R Nair Proceedings of the 28th annual international symposium on Microarchitecture …, 1995 | 191 | 1995 |
| A simple yet effective technique for global wiring R Nair IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1987 | 153 | 1987 |
| Active memory cube: A processing-in-memory architecture for exascale systems R Nair, SF Antao, C Bertolli, P Bose, JR Brunheroto, T Chen, CY Cher, ... IBM Journal of Research and Development 59 (2/3), 17: 1-17: 14, 2015 | 142 | 2015 |
| Method and system for transparent dynamic optimization in a multiprocessing environment R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener US Patent 7,146,607, 2006 | 121 | 2006 |
| Exploiting instruction level parallelism in processors by caching scheduled groups R Nair, ME Hopkins ACM SIGARCH Computer Architecture News 25 (2), 13-25, 1997 | 119 | 1997 |
| Comments on" An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" R Nair IEEE transactions on Computers 28 (3), 258-261, 1979 | 117 | 1979 |
| High speed machine for the physical design of very large scale integrated circuits SJ Hong, RK Nair, E Shapiro US Patent 4,484,292, 1984 | 108 | 1984 |
| Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,779,049, 2004 | 105 | 2004 |
| FactSheets: Increasing trust in AI services through supplier's declarations of conformity M Arnold, RKE Bellamy, M Hind, S Houde, S Mehta, A Mojsilović, R Nair, ... IBM Journal of Research and Development 63 (4/5), 6: 1-6: 13, 2019 | 88 | 2019 |
| Multiprocessor with pair-wise high reliability mode, and method therefore SH Dhong, HP Hofstee, R Nair, SD Posluszny US Patent 6,772,368, 2004 | 81 | 2004 |
| Programming with relaxed synchronization L Renganarayana, V Srinivasan, R Nair, D Prener Proceedings of the 2012 ACM workshop on Relaxing synchronization for …, 2012 | 80 | 2012 |
| Linear time algorithms for optimal CMOS layout R Nair, A Bruss, J Reif IBM Thomas J. Watson Research Division, 1983 | 76 | 1983 |
| Global wiring on a wire routing machine R Nair, SJ Hong, S Liles, R Villani 19th Design Automation Conference, 224-231, 1982 | 73 | 1982 |
| Method and system for multiprocessor emulation on a multiprocessor host system ER Altman, R Nair, JK O'brien, KM O'brien, PH Oden, DA Prener, ... US Patent 7,496,494, 2009 | 63 | 2009 |
| Big data needs approximate computing: technical perspective R Nair Communications of the ACM 58 (1), 104-104, 2014 | 56 | 2014 |
