Alexandre Levisse
Alexandre Levisse
Verified email at epfl.ch
Title
Cited by
Cited by
Year
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications
G Sassine, C Nail, L Tillie, DA Robayo, A Levisse, C Cagli, KE Hajjam, ...
2018 IEEE International Reliability Physics Symposium (IRPS), P-MY. 2-1-P-MY†…, 2018
222018
Sneakpath compensation circuit for programming and read operations in rram-based crosspoint architectures
A Levisse, B Giraud, JP Noel, M Moreau, JM Portal
2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015
182015
In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors
M Alayan, E Vianello, G Navarro, C Carabasse, S La Barbera, A Verdy, ...
2017 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2017
142017
Architecture, design and technology guidelines for crosspoint memories
A Levisse, B Giraud, JP Noel, M Moreau, JM Portal
2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH†…, 2017
132017
Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2)/28 nm FDSOI CMOS technology
JM Portal, M Bocquet, S Onkaraiah, M Moreau, H Aziza, D Deleruyelle, ...
IEEE Transactions on Nanotechnology 16 (4), 677-686, 2017
122017
A fast, reliable and wide-voltage-range in-memory computing architecture
W Simon, J Galicia, A Levisse, M Zapater, D Atienza
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
92019
BLADE: A bitline accelerator for devices on the edge
WA Simon, YM Qureshi, A Levisse, M Zapater, D Atienza
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 207-212, 2019
92019
High density emerging resistive memories: What are the limits?
A Levisse, B Giraud, JP NoŽl, M Moreau, JM Portal
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017
82017
Switching event detection and self-termination programming circuit for energy efficient reram memory arrays
M Alayan, E Muhr, A Levisse, M Bocquet, M Moreau, E Nowak, G Molas, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (5), 748-752, 2019
72019
New perspectives for multicore architectures using advanced technologies
F Clermidy, P Vivet, D Dutoit, Y Thonnart, JL Gonzales, JP NoŽl, B Giraud, ...
2016 IEEE International Electron Devices Meeting (IEDM), 35.1. 1-35.1. 4, 2016
72016
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures
A Levisse, B Giraud, JP Noel, M Moreau, JM Portal
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH†…, 2016
72016
Vertical CBRAM (V-CBRAM): from experimental data to design perspectives
G Piccolboni, M Parise, G Molas, A Levisse, JM Portal, R Coquand, ...
2016 IEEE 8th International Memory Workshop (IMW), 1-4, 2016
72016
Rram-vac: A variability-aware controller for rram-based memory architectures
S Tuli, M Rios, A Levisse, DA ESL
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 181-186, 2020
62020
Advanced memory solutions for emerging circuits and systems
B Giraud, A Makosiej, R Boumchedda, N Gupta, A Levisse, E Vianello, ...
2017 IEEE International Electron Devices Meeting (IEDM), 19.4. 1-19.4. 4, 2017
52017
Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications
G Molas, G Piccolboni, M Barci, B Traore, J Guy, G Palma, E Vianello, ...
2016 International Symposium on VLSI Technology, Systems and Application†…, 2016
52016
BLADE: An in-Cache Computing Architecture for Edge Devices
WA Simon, YM Qureshi, M Rios, A Levisse, M Zapater, D Atienza
IEEE Transactions on Computers 69 (9), 1349-1363, 2020
42020
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination
SB Krit, W Rahajandraibe, K Castellani-Couliť, G Micolau, A Levisse, ...
2014 15th Latin American Test Workshop-LATW, 1-6, 2014
42014
Resistive switching memory architecture based on polarity controllable selectors
A Levisse, PE Gaillardon, B Giraud, I O'Connor, JP Noel, M Moreau, ...
IEEE Transactions on Nanotechnology 18, 183-194, 2018
32018
Functionality Enhanced Memories for Edge-AI Embedded Systems
A Levisse, M Rios, WA Simon, PE Gaillardon, D Atienza
2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2019
22019
An associativity-agnostic in-cache computing architecture optimized for multiplication
M Rios, W Simon, A Levisse, M Zapater, D Atienza
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration†…, 2019
22019
The system can't perform the operation now. Try again later.
Articles 1–20