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Nadereh Hatami
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Multi-layer diagnosis for fault-tolerant networks-on-chip
G Schley, A Dalirsani, M Eggenberger, N Hatami, HJ Wunderlich, ...
IEEE Transactions on Computers 66 (5), 848-861, 2016
162016
Efficient simulation of structural faults for the reliability evaluation at system-level
MA Kochte, CG Zoellin, R Baranowski, ME Imhof, HJ Wunderlich, ...
2010 19th IEEE Asian Test Symposium, 3-8, 2010
152010
Efficient multi-level fault simulation of HW/SW systems for structural faults
R Baranowski, S Di Carlo, N Hatami, ME Imhof, MA Kochte, P Prinetto, ...
Science China Information Sciences 54, 1784-1796, 2011
122011
Multilevel simulation of nonfunctional properties by piecewise evaluation
N Hatami, R Baranowski, P Prinetto, HJ Wunderlich
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (4 …, 2014
82014
TLM 2.0 simple sockets synthesis to RTL
N Hatami, A Ghofrani, P Prinetto, Z Navabi
2009 4th International Conference on Design & Technology of Integrated …, 2009
72009
On covering structural defects in NoCs by functional tests
A Dalirsani, N Hatami, ME Imhof, M Eggenberger, G Schley, M Radetzki, ...
2014 IEEE 23rd Asian Test Symposium, 87-92, 2014
52014
Efficient system-level aging prediction
N Hatami, R Baranowski, P Prinetto, HJ Wunderlich
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
52012
Communication interface synthesis from TLM 2.0 to RTL
N Hatami, M Indaco, P Prinetto, G Tiotto
2010 East-West Design & Test Symposium (EWDTS), 222-226, 2010
42010
Hardware design methodology to synthesize communication interfaces from TLM to RTL
N Hatami, P Prinetto, A Trapanese
2010 IEEE International Conference on Automation, Quality and Testing …, 2010
42010
Sign language synthesis using hand motion acquisition
N Hatami, P Prinetto, G Tiotto
2010 East-West Design & Test Symposium (EWDTS), 226-229, 2010
22010
System reliability evaluation using concurrent multi-level simulation of structural faults
MA Kochte, CG Zoellin, R Baranowski, ME Imhof, HJ Wunderlich, ...
2010 IEEE International Test Conference, 1-1, 2010
12010
System Level Testing via TLM 2.0 Debug Transport Interface
S Di Carlo, N Hatami, P Prinetto, A Savino
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009
12009
An Editor for Assisted Translation of Italian Sign
N Hatami, P Prinetto, G Tiotto
2020
Functional Tests
A Dalirsani, N Hatami, ME Imhof, M Eggenberger, G Schley, M Radetzki, ...
2014
Multi-level analysis of non-functional properties
N Hatami Mazinani
2014
Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene
MA Kochte, CG Zöllin, R Baranowski, ME Imhof, HJ Wunderlich, N Hatami, ...
GMM/GI/ITG-Fachtagung 13, 25-32, 2010
2010
Test infrastructures evaluation at transaction level
S Di Carlo, N Hatami, P Prinetto
2009 International Test Conference, 1-1, 2009
2009
An advanced method for synthesizing TLM2-based interfaces
N Hatami, Z Navabi
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08), 104-108, 2008
2008
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Articles 1–18