| Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI T Morimoto, T Ohguro, S Momose, T Iinuma, I Kunishima, K Suguro, ... IEEE Transactions on Electron Devices 42 (5), 915-922, 1995 | 390 | 1995 |
| Future perspective and scaling down roadmap for RF CMOS E Morifuji, HS Momose, T Ohguro, T Yoshitomi, H Kimijima, F Matsuoka, ... 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 1999 | 159 | 1999 |
| A NiSi salicide technology for advanced logic devices T Morimoto, HS Momose, T Iinuma, I Kunishima, K Suguro, H Okana, ... International Electron Devices Meeting 1991 [Technical Digest], 653-656, 1991 | 139 | 1991 |
| An 0.18-/spl mu/m CMOS for mixed digital and analog applications with zero-volt-V/sub th/epitaxial-channel MOSFETs T Ohguro, H Naruse, H Sugaya, E Morifuji, S Nakamura, T Yoshitomi, ... IEEE Transactions on Electron Devices 46 (7), 1378-1383, 1999 | 137 | 1999 |
| Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: Uniformity, reliability, and dopant penetration of the gate oxide HS Momose, SI Nakamura, T Ohguro, T Yoshitomi, E Morifuji, T Morimoto, ... IEEE transactions on electron devices 45 (3), 691-700, 1998 | 137 | 1998 |
| High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs HS Momose, E Morifuji, T Yoshitomi, T Ohguro, I Saito, T Morimoto, ... International Electron Devices Meeting. Technical Digest, 105-108, 1996 | 125 | 1996 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... IEEE Transactions on Electron Devices 49 (12), 2263-2270, 2002 | 74 | 2002 |
| A novel lateral bipolar transistor with 67 GHz f/sub max/on thin-film SOI for RF analog applications H Nii, T Yamada, K Inoh, T Shino, S Kawanaka, M Yoshimi, Y Katsumata IEEE Transactions on electron devices 47 (7), 1536-1541, 2000 | 73 | 2000 |
| Manufacturing method of semiconductor device comprising BiCMOS transistor K Inoh, Y Katsumata, S Matsuda, C Yoshino US Patent 5,620,908, 1997 | 58 | 1997 |
| High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE S Inaba, K Okano, S Matsuda, M Fujiwara, A Hokazono, K Adachi, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 51 | 2001 |
| High performance RF characteristics of raised gate/source/drain CMOS with Co salicide T Ohguro, H Naruse, H Sugaya, S Nakamura, E Morifuji, H Kimijima, ... 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No …, 1998 | 51 | 1998 |
| A study of hot-carrier degradation in n-and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime HS Momose, SI Nakamura, T Ohguro, T Yoshitomi, E Morifuji, T Morimoto, ... International Electron Devices Meeting. IEDM Technical Digest, 453-456, 1997 | 41 | 1997 |
| Thermal stability of CoSi/sub 2/film for CMOS salicide T Ohguro, M Saito, E Morifuji, T Yoshitomi, T Morimoto, HS Momose, ... IEEE Transactions on Electron Devices 47 (11), 2208-2213, 2000 | 39 | 2000 |
| The future of ultra-small-geometry MOSFETs beyond 0.1 micron H Iwai, HS Momose, M Saito, M Ono, Y Katsumata Microelectronic Engineering 28 (1-4), 147-154, 1995 | 39 | 1995 |
| A study of flicker noise in n-and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime HS Momose, H Kimijima, S Ishizuka, Y Miyahara, T Ohguro, T Yoshitomi, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 37 | 1998 |
| Method of manufacturing bipolar semiconductor device Y Katsumata, T Ito US Patent 4,782,030, 1988 | 36 | 1988 |
| A 31 GHz f/sub max/lateral BJT on SOI using self-aligned external base formation technology T Shino, K Inoh, T Yamada, H Nii, S Kawanaka, T Fuse, M Yoshimi, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 34 | 1998 |
| Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating T Ohguro, N Sugiyama, S Imai, K Usuda, M Saito, T Yoshitomi, M Ono, ... IEEE Transactions on Electron Devices 45 (3), 710-716, 1998 | 32 | 1998 |
| On-chip spiral inductors with diffused shields using channel-stop implant T Yoshitomi, Y Sugawara, E Morifuji, T Ohguro, H Kimijima, T Morimoto, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 30 | 1998 |
| An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics Saito, Yoshitomi, Ono, Akasaka, Nii, Matsuda, Momose, Katsumata, ... 1992 International Technical Digest on Electron Devices Meeting, 897-900, 1992 | 30 | 1992 |
