Dennis Han Chung Lin
Dennis Han Chung Lin
Verified email at imec.be
Title
Cited by
Cited by
Year
Leakage current and breakdown electric-field studies on ultrathin atomic-layer-deposited on GaAs
HC Lin, PD Ye, GD Wilk
Applied physics letters 87 (18), 182904, 2005
2462005
Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Depositedas Gate Dielectric
Y Xuan, YQ Wu, HC Lin, T Shen, DY Peide
IEEE Electron Device Letters 28 (11), 935-938, 2007
2132007
Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited AI2O3 gate dielectric
Y Xuan, HC Lin, PD Ye, GD Wilk
APPLIED PHYSICS LETTERS 88, 263518, 2006
2022006
Germanium surface passivation and atomic layer deposition of high-k dielectrics—A tutorial review on Ge-based MOS capacitors
Q Xie, S Deng, M Schaekers, D Lin, M Caymax, A Delabie, XP Qu, ...
Semiconductor Science and Technology 27 (7), 074012, 2012
1442012
Capacitance-voltage characterization of interfaces
G Brammertz, HC Lin, K Martens, D Mercier, S Sioncke, A Delabie, ...
Applied Physics Letters 93 (18), 183504, 2008
1322008
Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High-Dielectrics
Y Xuan, HC Lin, DY Peide
IEEE Transactions on electron devices 54 (8), 1811-1817, 2007
1182007
On the interface state density at /oxide interfaces
G Brammertz, HC Lin, M Caymax, M Meuris, M Heyns, M Passlack
Applied Physics Letters 95 (20), 202109, 2009
1142009
Electrical study of sulfur passivated In0. 53Ga0. 47As MOS capacitor and transistor with ALD Al2O3 as gate insulator
HC Lin, WE Wang, G Brammertz, M Meuris, M Heyns
Microelectronic Engineering 86 (7-9), 1554-1557, 2009
1132009
A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied toand InP Capacitors
G Brammertz, A Alian, DHC Lin, M Meuris, M Caymax, WE Wang
IEEE Transactions on Electron Devices 58 (11), 3890-3897, 2011
1052011
Capacitance–voltage characterization of GaAs–oxide interfaces
G Brammertz, HC Lin, K Martens, D Mercier, C Merckling, J Penaud, ...
Journal of the Electrochemical Society 155 (12), H945, 2008
812008
The Fermi-level efficiency method and its applications on high interface trap density oxide-semiconductor interfaces
HC Lin, G Brammertz, K Martens, G de Valicourt, L Negre, WE Wang, ...
Applied physics letters 94 (15), 153508, 2009
752009
Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited as gate dielectric
HC Lin, T Yang, H Sharifi, SK Kim, Y Xuan, T Shen, S Mohammadi, PD Ye
Applied Physics Letters 91 (21), 212101, 2007
722007
Electrical properties of III-V/oxide interfaces
G Brammertz, HC Lin, K Martens, AR Alian, C Merckling, J Penaud, ...
ECS transactions 19 (5), 375, 2009
712009
Border traps in Ge/III–V channel devices: Analysis and reliability aspects
E Simoen, DHC Lin, A Alian, G Brammertz, C Merckling, J Mitard, ...
IEEE Transactions on Device and Materials Reliability 13 (4), 444-455, 2013
682013
Enabling the high-performance InGaAs/Ge CMOS: A common gate stack solution
D Lin, G Brammertz, S Sioncke, C Fleischmann, A Delabie, K Martens, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
682009
Advancing CMOS beyond the Si roadmap with Ge and III/V devices
M Heyns, A Alian, G Brammertz, M Caymax, YC Chang, LK Chu, ...
2011 International Electron Devices Meeting, 13.1. 1-13.1. 4, 2011
652011
Interfaces of high-k dielectrics on GaAs: Their common features and the relationship with Fermi level pinning
M Caymax, G Brammertz, A Delabie, S Sioncke, D Lin, M Scarrozza, ...
Microelectronic engineering 86 (7-9), 1529-1535, 2009
642009
Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3
J Franco, A Alian, B Kaczer, D Lin, T Ivanov, A Pourghaderi, K Martens, ...
2014 IEEE International Reliability Physics Symposium, 6A. 2.1-6A. 2.6, 2014
592014
Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow
N Waldron, S Sioncke, J Franco, L Nyns, A Vais, X Zhou, HC Lin, ...
2015 IEEE International Electron Devices Meeting (IEDM), 31.1. 1-31.1. 4, 2015
532015
Polarity control in WSe2 double-gate transistors
GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ...
Scientific reports 6, 29448, 2016
512016
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Articles 1–20