| Customizable embedded processors: design technologies and applications P Ienne, R Leupers Elsevier, 2006 | 208 | 2006 |
| NoCGEN: A template based reuse methodology for networks on chip architecture J Chan, S Parameswaran 17th International Conference on VLSI Design. Proceedings., 717-720, 2004 | 113 | 2004 |
| GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis H Gamaarachchi, CW Lam, G Jayatilaka, H Samarakoon, JT Simpson, ... BMC bioinformatics 21, 1-13, 2020 | 97 | 2020 |
| Embedded systems security—an overview S Parameswaran, T Wolf Design Automation for Embedded Systems 12, 173-183, 2008 | 91 | 2008 |
| Minimally biased multipliers for approximate integer and floating-point multiplication H Saadat, H Bokhari, S Parameswaran IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 87 | 2018 |
| RIJID: Random code injection to mask power analysis based side channel attacks JA Ambrose, RG Ragel, S Parameswaran Proceedings of the 44th annual Design Automation Conference, 489-492, 2007 | 87 | 2007 |
| Design methodology for pipelined heterogeneous multiprocessor system SL Shee, S Parameswaran Proceedings of the 44th annual Design Automation Conference, 811-816, 2007 | 86 | 2007 |
| IMPRES: integrated monitoring for processor reliability and security RG Ragel, S Parameswaran Proceedings of the 43rd annual Design Automation Conference, 502-505, 2006 | 86 | 2006 |
| Finding optimal L1 cache configuration for embedded systems A Janapsatya, A Ignjatović, S Parameswaran Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 86 | 2006 |
| Fast nanopore sequencing data analysis with SLOW5 H Gamaarachchi, H Samarakoon, SP Jenner, JM Ferguson, TG Amos, ... Nature biotechnology 40 (7), 1026-1029, 2022 | 83 | 2022 |
| darknoc: Designing energy-efficient network-on-chip with multi-vt cells for dark silicon H Bokhari, H Javaid, M Shafique, J Henkel, S Parameswaran Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 74 | 2014 |
| A novel instruction scratchpad memory optimization method based on concomitance metric A Janapsatya, A Ignjatović, S Parameswaran Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 72 | 2006 |
| Dark silicon as a challenge for hardware/software co-design: Invited special session paper M Shafique, S Garg, T Mitra, S Parameswaran, J Henkel Proceedings of the 2014 International Conference on Hardware/Software …, 2014 | 71 | 2014 |
| Embedded software for SoC AA Jerraya | 68 | 2003 |
| NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks J Chan, S Parameswaran 2008 Asia and South Pacific Design Automation Conference, 265-270, 2008 | 63 | 2008 |
| MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm JA Ambrose, S Parameswaran, A Ignjatovic 2008 IEEE/ACM International Conference on Computer-Aided Design, 678-684, 2008 | 62 | 2008 |
| Hardware/software managed scratchpad memory for embedded system A Janapsatya, S Parameswaran, A Ignjatovic IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 61 | 2004 |
| NoCEE: energy macro-model extraction methodology for network on chip routers J Chan, S Parameswaran ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 60 | 2005 |
| Inside: Instruction selection/identification & design exploration for extensible processors N Cheung, S Parameswaran, J Henkel ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 59 | 2003 |
| Rapid configuration and instruction selection for an ASIP: a case study N Cheung, J Henkel, S Parameswaran 2003 Design, Automation and Test in Europe Conference and Exhibition, 802-807, 2003 | 54 | 2003 |
