Steven Derrien

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	All	Since 2016
Citations	1629	647
h-index	19	12
i10-index	42	15

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Co-authors

Olivier SentieysProfessor, University of Rennes, IRISA, INRIA, FranceVerified email at irisa.fr
Sanjay RajopadhyeColorado State UniversityVerified email at colostate.edu
Tomofumi YukiInriaVerified email at inria.fr
Muhammad Adeel PashaDepartment of Electrical Engineering, LUMS, PakistanVerified email at lums.edu.pk
Benoit CombemaleProfessor of Software Engineering at University of Rennes 1Verified email at irisa.fr
George GoulasComputer Systems Laboratory, University of PatrasVerified email at ece.upatras.gr
Jean-Marc JezequelProfessor of Software Engineering, Univ Rennes, CNRS, Inria, IRISAVerified email at irisa.fr
Rubini StéphaneMaître de Conférences, Université de Bretagne OccidentaleVerified email at univ-brest.fr
Susmita Sur-KolayProfessor of Computer ScienceVerified email at isical.ac.in
Daniel MENARDUBL, INSA/IETRVerified email at insa-rennes.fr
Dr. Frédéric RaimbaultAssociate Professor, University of South Brittany, F-56017 Vannes, FranceVerified email at irisa.fr
François CharotINRIA RennesVerified email at inria.fr
Jim SteelSoftware Engineer, Australian e-Health Research Centre, CSIROVerified email at csiro.au
Robert FranceProfessor of Computer Science, Colorado State UniversityVerified email at cs.colostate.edu
Mathieu GiraudSenior Researcher, CNRS, CRIStAL, Université Lille, InriaVerified email at univ-lille.fr
Naeem AbbasNational University of Sciences & Technology, PakistanVerified email at pnec.nust.edu.pk
Rayan ChikhiInstitut Pasteur & CNRSVerified email at ens-cachan.org
Bart KienhuisAssistant Professor of Computer Science, Leiden UniversityVerified email at liacs.nl

Steven Derrien

Université de Rennes 1

Verified email at irisa.fr


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
High-level synthesis: from algorithm to digital circuit P Coussy, A Morawiec Springer, 2008	488	2008
On model subtyping C Guy, B Combemale, S Derrien, JRH Steel, JM Jézéquel European Conference on Modelling Foundations and Applications, 400-415, 2012	76	2012
Approximating a single viewpoint in panoramic imaging devices S Derrien, K Konolige Proceedings 2000 ICRA. Millennium Conference. IEEE International Conference …, 2000	74	2000
ompVerify: polyhedral analysis for the OpenMP programmer V Basupalli, T Yuki, S Rajopadhye, A Morvan, S Derrien, P Quinton, ... International Workshop on OpenMP, 37-53, 2011	54	2011
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking MA Pasha, S Derrien, O Sentieys Design Automation Conference, 693-698, 2010	43	2010
Polyhedral bubble insertion: A method to improve nested loop pipelining for high-level synthesis A Morvan, S Derrien, P Quinton IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013	40	2013
Tightening contention delays while scheduling parallel applications on multi-core architectures B Rouxel, S Derrien, I Puaut ACM Transactions on Embedded Computing Systems (TECS) 16 (5s), 1-20, 2017	38	2017
Runtime dependency analysis for loop pipelining in high-level synthesis M Alle, A Morvan, S Derrien Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013	38	2013
Parallelizing HMMER for hardware acceleration on FPGAs S Derrien, P Quinton 2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007	35	2007
GeCoS: A framework for prototyping custom hardware design flows A Floc'h, T Yuki, A El-Moussawi, A Morvan, K Martin, M Naullet, M Alle, ... 2013 IEEE 13th International Working Conference on Source Code Analysis and …, 2013	34	2013
Combined instruction and loop parallelism in array synthesis for FPGAs S Derrien, S Rajopadhye, SS Kolay Proceedings of the 14th international symposium on Systems synthesis, 165-170, 2001	32*	2001
A Reconfigurable Parallel Disk System for Filtering Genomic Banks. D Lavenier, S Guyetant, S Derrien, S Rubini Engineering of Reconfigurable Systems and Algorithms 2, 154-166, 2003	30	2003
HLS tools for FPGA: Faster development with better performance A Cornu, S Derrien, D Lavenier International Symposium on Applied Reconfigurable Computing, 67-78, 2011	26	2011
Loop tiling for reconfigurable accelerators S Derrien, S Rajopadhye International Conference on Field Programmable Logic and Applications, 398-408, 2001	24	2001
Acceleration of a content-based image-retrieval application on the RDISK cluster A Noumsi, S Derrien, P Quinton Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006	23	2006
Cluster of re-configurable nodes for scanning large genomic banks S Guyetant, M Giraud, L L’Hours, S Derrien, S Rubini, D Lavenier, ... Parallel Computing 31 (1), 73-96, 2005	23	2005
Toward ultra low-power hardware specialization of a wireless sensor network node MA Pasha, S Derrien, O Sentieys 2009 IEEE 13th International Multitopic Conference, 1-6, 2009	22	2009
Method and apparatus for panoramic imaging K Konolige, S Derrien US Patent 6,545,702, 2003	21	2003
High-level synthesis of loops using the polyhedral model S Derrien, S Rajopadhye, P Quinton, T Risset High-level synthesis, 215-230, 2008	20	2008
Hardware acceleration of HMMER on FPGAs S Derrien, P Quinton Journal of Signal Processing Systems 58 (1), 53, 2010	18	2010

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