Jiwoo Pak
Jiwoo Pak
Verified email at google.com
Title
Cited by
Cited by
Year
Modeling of electromigration in through-silicon-via based 3D IC
J Pak, M Pathak, SK Lim, DZ Pan
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 1420 …, 2011
742011
Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs
M Pathak, J Pak, DZ Pan, SK Lim
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 555-562, 2011
502011
Chip placement with deep reinforcement learning
A Mirhoseini, A Goldie, M Yazgan, J Jiang, E Songhori, S Wang, YJ Lee, ...
arXiv preprint arXiv:2004.10746, 2020
442020
Design for manufacturability and reliability for TSV-based 3D ICs
DZ Pan, SK Lim, K Athikulwongse, M Jung, J Mitra, J Pak, M Pathak, ...
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012
362012
Robust clock tree synthesis with timing yield optimization for 3D-ICs
JS Yang, J Pak, X Zhao, SK Lim, DZ Pan
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 621-626, 2011
332011
Electromigration study for multiscale power/ground vias in TSV-based 3-D ICs
J Pak, SK Lim, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
312014
Electromigration-aware redundant via insertion
J Pak, B Yu, DZ Pan
The 20th Asia and South Pacific Design Automation Conference, 544-549, 2015
172015
Electromigration-aware routing for 3D ICs with stress-aware EM modeling
J Pak, SK Lim, DZ Pan
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 325-332, 2012
142012
A frequency tunable resonant clock distribution scheme using bond-wire inductor
W Lee, JS Pak, J Pak, C Ryu, J Park, J Kim
2008 Electrical Design of Advanced Packaging and Systems Symposium, 24-26, 2008
62008
Design of a 3-D SiP for T-DMB with Improvement of Sensitivity and Noise Isolation
J Pak, M Ha, J Kim, D Kang, H Choi, S Kwon, K La, J Kim
2008 10th Electronics Packaging Technology Conference, 1387-1392, 2008
52008
Soft-remote-control system based on emg signals for the intelligent sweet home
JH Song, JS Han, JW Pak, DJ Kim, JW Jung, ZZ Bien, HY Lee
제어로봇시스템학회: 학술대회논문집, 1163-1168, 2005
42005
A graph placement methodology for fast chip design
A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ...
Nature 594 (7862), 207-212, 2021
12021
Electromigration modeling and layout optimization for advanced VLSI
J Pak
2014
A Frequency Clock Distribution Scheme Using Bond-Wire Inductor
J Kim, W Lee, JS Pak, J Pak, C Ryu, J Park
IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2008
2008
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Articles 1–14