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Cited by
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Since 2019
Citations
52
52
h-index
4
4
i10-index
3
3
0
24
12
2020
2021
2022
2023
2024
2
12
9
24
5
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Co-authors
Rahul Shrestha
Associate Professor, IIT Mandi
Verified email at iitmandi.ac.in
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Anuj Verma
Ph.D Research Scholar
Verified email at students.iitmandi.ac.in
LDPC and Polar codes
Digital VLSI Architectures
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Year
A new VLSI architecture of next-generation QC-LDPC decoder for 5G new-radio wireless-communication standard
A Verma, R Shrestha
2020 IEEE international symposium on circuits and systems (ISCAS), 1-5
, 2020
15
2020
A new partially-parallel VLSI-architecture of quasi-cyclic LDPC decoder for 5G new-radio
A Verma, R Shrestha
2020 33rd International Conference on VLSI Design and 2020 19th …
, 2020
15
2020
Low computational-complexity SOMS-algorithm and high-throughput decoder architecture for QC-LDPC codes
A Verma, R Shrestha
IEEE Transactions on Vehicular Technology 72 (1), 66-80
, 2022
14
2022
Hardware-efficient and high-throughput LLRC segregation based binary QC-LDPC decoding algorithm and architecture
A Verma, R Shrestha
IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2835-2839
, 2021
8
2021
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard
A Verma, R Shrestha
VLSID 2020
A Verma, R Shrestha, V Tyagi, V Rana, F Loh, KK Saluja
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