Jürgen Maier
Jürgen Maier
Verified email at tuwien.ac.at - Homepage
Title
Cited by
Cited by
Year
The metastable behavior of a Schmitt-Trigger
A Steininger, J Maier, R Najvirt
2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems …, 2016
52016
Modeling the CMOS inverter using hybrid systems
J Maier
E182-Institut für Technische Informatik, 2017
42017
Verifying nonlinear analog and mixed-signal circuits with inputs
C Fan, Y Meng, J Maier, E Bartocci, S Mitra, U Schmid
IFAC-PapersOnLine 51 (16), 241-246, 2018
32018
A faithful binary circuit model with adversarial noise
M Függer, J Maier, R Najvirt, T Nowak, U Schmid
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
22018
Atomistic modeling of interfaces in III–V semiconductor superlattices
J Maier, H Detz
physica status solidi (b) 253 (4), 613-622, 2016
12016
The Involution Tool for Accurate Digital Timingand Power Analysis
D Öhlinger, J Maier, M Függer, U Schmid
2019 29th International Symposium on Power and Timing Modeling, Optimization …, 2019
2019
Unified (A) Synchronous Circuit Development
P Paulweber, J Maier, J Cortadella
2019
Transistor-Level Analysis of Dynamic Delay Models
J Maier, M Függer, T Nowak, U Schmid
2019 25th IEEE International Symposium on Asynchronous Circuits and Systems …, 2019
2019
Efficient Metastability Characterization for Schmitt-Triggers
J Maier, A Steininger
2019 25th IEEE International Symposium on Asynchronous Circuits and Systems …, 2019
2019
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
A Steininger, R Najvirt, J Maier
2016 Euromicro Conference on Digital System Design (DSD), 372-379, 2016
2016
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic
J Maier, A Steininger
17th International Symposium on Design and Diagnostics of Electronic …, 2014
2014
Bachelor thesis Powerline in Building Automation
J Maier
2011
" Online Test Vector Insertion-A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic"; Betreuer/in (nen): A. Steininger; Technische Informatik, 2014.
J Maier
Atomistic Interface Modeling in III-V Semiconductor Superlattices
J Maier, G Strasser, H Detz
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Articles 1–14