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Carl Ramey
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Cited by
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On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
12072007
Tile64-processor: A 64-core soc with mesh interconnect
S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
8552008
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
3732014
Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor
S Taylor, M Quinn, D Brown, N Dohm, S Hildebrandt, J Huggins, C Ramey
Proceedings of the 35th annual Design Automation Conference, 638-643, 1998
1301998
High performance, scalable multi chip interconnect
CG Ramey, M Mattina
US Patent 9,424,228, 2016
1172016
Coupling integrated circuits in a parallel processing environment
D Wentzlaff, CG Ramey, A Agarwal
US Patent 7,539,845, 2009
992009
Tile-gx100 manycore processor: Acceleration interfaces and architecture
C Ramey
2011 IEEE Hot Chips 23 Symposium (HCS), 1-21, 2011
952011
Tile processor: Embedded multicore for networking and multimedia
A Agarwal, L Bao, J Brown, B Edwards, M Mattina, CC Miao, C Ramey, ...
Hot Chips 19, 2007
832007
Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip
C Ramey
US Patent 7,552,241, 2009
662009
Silicon Photonics for Artificial Intelligence Acceleration: HotChips 32
C Ramey
2020 IEEE Hot Chips 32 Symposium (HCS), 1-26, 2020
552020
Photonic processing systems and methods
D Bunandar, NC Harris, C Ramey
US Patent 10,763,974, 2020
442020
Condensed router headers with low latency output port calculation
IR Bratt, CG Ramey, M Mattina
US Patent 8,572,353, 2013
372013
Coupling data in a parallel processing environment
CG Ramey, D Wentzlaff, A Agarwal
US Patent 7,636,835, 2009
332009
Dual slot-mode NOEM phase shifter
R Baghdadi, M Gould, S Gupta, M Tymchenko, D Bunandar, C Ramey, ...
Optics Express 29 (12), 19113-19119, 2021
322021
Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors
MC Mattina, C Ramey, B Jung, J Leonard
US Patent 7,620,954, 2009
312009
Managing cache access and streaming data
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent App. 10/210,092, 2019
23*2019
Computing in parallel processing environments
CG Ramey, CD Metcalf
US Patent App. 10/037,299, 2018
21*2018
Managing cache coherence
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent 8,521,963, 2013
202013
Managing cache access and streaming data
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent 9,213,652, 2015
172015
Power supply voltage monitoring and high-resolution adaptive clock stretching circuit
A Carlson, C Ramey
US Patent 10,148,258, 2018
152018
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