| All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters S Chen, L Wang, H Zhang, A Chan Carusone IEEE Transactions on Very Large Scale Integration Systems, 2017 | 67 | 2017 |
| A Nano-Watt MOS-Only Voltage Reference with High-Slope PTAT Voltage Generators H Zhang, S Chen, A Chan Carusone the IEEE Transactions on Circuits and Systems II: Express Briefs, 2017 | 65 | 2017 |
| A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects S Chen, H Li, PY Chiang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 578-586, 2016 | 23 | 2016 |
| A 0.8 V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS H Li, S Chen, L Yang, R Bai, W Hu, FY Zhong, S Palermo, PY Chiang 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 23 | 2014 |
| Godson-3B1500: A 32nm 1.35 GHz 40W 172.8 GFLOPS 8-core processor W Hu, Y Zhang, L Yang, B Fan, Y Chen, S Zhong, H Wang, Z Qi, P Wang, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 18 | 2013 |
| A low-power high-swing voltage-mode transmitter S Chen, H Li, X Shi, L Yang, Z Yang, S Zhong, L Huang Journal of Semiconductors 33 (4), 045003, 2012 | 11* | 2012 |
| A novel SST transmitter with mutually decoupled impedance self-calibration and equalization S Chen, L Yang, H Jing, F Zhang, Z Gao 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 173-176, 2011 | 11 | 2011 |
| A 1.2 pJ/b 6.4 Gb/s 8+ 1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS S Chen, H Li, L Yang, Z Yang, W Hu, PY Chiang Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 7 | 2013 |
| A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line S Chen, H Li, K Jia, Y Wang, X Shi, F Zhang 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1803-1806, 2012 | 4 | 2012 |
| An 8Gb/s 0.75mW/Gb/s Injection-Locked Receiver with Constant Jitter Tracking Bandwidth and Accurate Quadrature Clock Generation in 40nm CMOS S Chen, Q Ao, H Jing, X Shi, S Meng, C Xinke Electronics, Circuits, and Systems (ICECS), 2014 21st IEEE International …, 2014 | 3 | 2014 |
| Optimizing memory access with fast address computation on a mips architecture Q Ao, G Jin, W Su, S Cai, S Chen 2014 9th IEEE International Conference on Networking, Architecture, and …, 2014 | 2 | 2014 |
| Alpha Compression with Variable Data Formats Y Jiang11, MGS Chen, W Hu | 1 | 2011 |
| All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters S Chen, L Wang, H Zhang, R Murugesu, D Dunwell, AC Carusone ISCAS 2018, 2018 | | 2018 |
| Multi-phase delay phase-locked loop and control method S Chen, P Zhao, S Meng, Z Shiqiang CN Patent CN103,441,757, 2016 | | 2016 |
| Digital delay device S Chen, H Li, Z Shiqiang CN Patent CN102,664,623, 2015 | | 2015 |
| 一个低功耗高摆幅电压模式发送端 C Shuai, L Hao, S Xiaobing, Y Liqiong, Y Zongren, Z Shiqiang, H Lingyi Journal of Semiconductors 33 (4), 045003-6, 2012 | | 2012 |
