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Narendra Parihar
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Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors
SS Cheema, N Shanker, LC Wang, CH Hsu, SL Hsu, YH Liao, ...
Nature 604 (7904), 65-71, 2022
1232022
BTI analysis tool—Modeling of NBTI DC, AC stress and recovery time kinetics, nitrogen impact, and EOL estimation
N Parihar, N Goel, S Mukhopadhyay, S Mahapatra
IEEE Transactions on Electron Devices 65 (2), 392-403, 2017
1132017
Ultrafast measurements and physical modeling of NBTI stress and recovery in RMG FinFETs under diverse DC–AC experimental conditions
N Parihar, U Sharma, RG Southwick, M Wang, JH Stathis, S Mahapatra
IEEE Transactions on Electron Devices 65 (1), 23-30, 2017
712017
A review of NBTI mechanisms and models
S Mahapatra, N Parihar
Microelectronics Reliability 81, 127-135, 2018
692018
A modeling framework for NBTI degradation under dynamic voltage and frequency scaling
N Parihar, N Goel, A Chaudhary, S Mahapatra
IEEE Transactions on Electron Devices 63 (3), 946-953, 2016
642016
Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, part-I: DC stress and recovery
N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra
IEEE Transactions on Electron Devices 65 (5), 1699-1706, 2018
472018
A 3-D TCAD framework for NBTI—Part I: Implementation details and FinFET channel material impact
R Tiwari, N Parihar, K Thakor, HY Wong, S Motzny, M Choi, V Moroz, ...
IEEE Transactions on Electron Devices 66 (5), 2086-2092, 2019
432019
Aging-aware voltage scaling
VM Van Santen, H Amrouch, N Parihar, S Mahapatra, J Henkel
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 576-581, 2016
412016
Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs
N Parihar, U Sharma, S Mukhopadhyay, N Goel, A Chaudhary, R Rao, ...
2017 IEEE International Reliability Physics Symposium (IRPS), XT-1.1-XT-1.11, 2017
352017
Modeling of NBTI using BAT framework: DC-AC stress-recovery kinetics, material, and process dependence
S Mahapatra, N Parihar
IEEE Transactions on Device and Materials Reliability 20 (1), 4-23, 2020
332020
A 3-D TCAD framework for NBTI, Part-II: Impact of mechanical strain, quantum effects, and FinFET dimension scaling
R Tiwari, N Parihar, K Thakor, HY Wong, S Motzny, M Choi, V Moroz, ...
IEEE Transactions on Electron Devices 66 (5), 2093-2099, 2019
312019
Consistency of the two component composite modeling framework for NBTI in large and small area p-MOSFETs
A Chaudhary, B Fernandez, N Parihar, S Mahapatra
IEEE Transactions on Electron Devices 64 (1), 256-263, 2016
292016
Modeling of NBTI kinetics in replacement metal gate Si and SiGe FinFETs—Part-II: AC stress and recovery
N Parihar, RG Southwick, M Wang, JH Stathis, S Mahapatra
IEEE Transactions on Electron Devices 65 (5), 1707-1713, 2018
282018
Device to circuit framework for activity-dependent nbti aging in digital circuits
A Thirunavukkarasu, H Amrouch, J Joe, N Goel, N Parihar, S Mishra, ...
IEEE Transactions on Electron Devices 66 (1), 316-323, 2018
272018
Modeling of DC-AC NBTI stress-recovery time kinetics in P-channel planar bulk and FDSOI MOSFETs and FinFETs
N Choudhury, N Parihar, N Goel, A Thirunavukkarasu, S Mahapatra
IEEE Journal of the Electron Devices Society 8, 1281-1288, 2020
252020
Key parameters driving transistor degradation in advanced strained SiGe channels
V Huard, C Ndiaye, M Arabi, N Parihar, X Federspiel, S Mhira, ...
2018 IEEE International Reliability Physics Symposium (IRPS), P-TX. 4-1-P-TX …, 2018
242018
Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs
N Parihar, RG Southwick, U Sharma, M Wang, JH Stathis, S Mahapatra
2017 IEEE International Reliability Physics Symposium (IRPS), 2D-4.1-2D-4.7, 2017
212017
A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs
T Samadder, N Choudhury, S Kumar, D Kochar, N Parihar, S Mahapatra
IEEE Transactions on Electron Devices 68 (2), 485-490, 2021
202021
A stochastic framework for the time kinetics of interface and bulk oxide traps for BTI, SILC, and TDDB in MOSFETs
S Kumar, R Anandkrishnan, N Parihar, S Mahapatra
IEEE Transactions on Electron Devices 67 (11), 4741-4748, 2020
202020
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
A Vandooren, Z Wu, N Parihar, J Franco, B Parvais, P Matagne, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
202020
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