| Deep learning with limited numerical precision S Gupta, A Agrawal, K Gopalakrishnan, P Narayanan International Conference on Machine Learning, 1737-1746, 2015 | 1311 | 2015 |
| Phase change memory technology GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ... Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2010 | 907 | 2010 |
| Overview of candidate device technologies for storage-class memory GW Burr, BN Kurdi, JC Scott, CH Lam, K Gopalakrishnan, RS Shenoy IBM Journal of Research and Development 52 (4.5), 449-464, 2008 | 846 | 2008 |
| I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q K Gopalakrishnan, PB Griffin, JD Plummer Digest. International Electron Devices Meeting,, 289-292, 2002 | 382 | 2002 |
| Activation and diffusion studies of ion-implanted and dopants in germanium CO Chui, K Gopalakrishnan, PB Griffin, JD Plummer, KC Saraswat Applied physics letters 83 (16), 3275-3277, 2003 | 355 | 2003 |
| Impact ionization MOS (I-MOS)-Part I: device and circuit simulations K Gopalakrishnan, PB Griffin, JD Plummer IEEE Transactions on electron devices 52 (1), 69-76, 2004 | 262 | 2004 |
| Pact: Parameterized clipping activation for quantized neural networks J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ... arXiv preprint arXiv:1805.06085, 2018 | 215 | 2018 |
| Training deep neural networks with 8-bit floating point numbers N Wang, J Choi, D Brand, CY Chen, K Gopalakrishnan Advances in neural information processing systems, 7675-7684, 2018 | 162 | 2018 |
| Specifications of nanoscale devices and circuits for neuromorphic computational systems B Rajendran, Y Liu, J Seo, K Gopalakrishnan, L Chang, DJ Friedman, ... IEEE Transactions on Electron Devices 60 (1), 246-253, 2012 | 153 | 2012 |
| Nanoscale electronic synapses using phase change devices BL Jackson, B Rajendran, GS Corrado, M Breitwisch, GW Burr, R Cheek, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-20, 2013 | 147 | 2013 |
| Impact ionization MOS (I-MOS)-part II: experimental results K Gopalakrishnan, R Woo, C Jungemann, PB Griffin, JD Plummer IEEE Transactions on Electron Devices 52 (1), 77-84, 2004 | 141 | 2004 |
| Rectifying element for a crosspoint based memory array architecture K Gopalakrishnan US Patent 8,203,873, 2012 | 130 | 2012 |
| Rectifying element for a crosspoint based memory array architecture K Gopalakrishnan US Patent 7,382,647, 2008 | 125 | 2008 |
| Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays K Gopalakrishnan, RS Shenoy, CT Rettner, K Virwani, DS Bethune, ... 2010 Symposium on VLSI Technology, 205-206, 2010 | 118 | 2010 |
| Adacomp: Adaptive residual gradient compression for data-parallel distributed training CY Chen, J Choi, D Brand, A Agrawal, W Zhang, K Gopalakrishnan Proceedings of the AAAI Conference on Artificial Intelligence 32 (1), 2018 | 74 | 2018 |
| Multi-bit high-density memory device and architecture and method of fabricating multi-bit high-density memory devices K Gopalakrishnan, RS Shenoy US Patent 7,763,932, 2010 | 69 | 2010 |
| Method and structure for increasing effective transistor width in memory arrays with dual bitlines GW Burr, K Gopalakrishnan US Patent 7,447,062, 2008 | 68 | 2008 |
| Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield GW Burr, K Virwani, RS Shenoy, A Padilla, M BrightSky, EA Joseph, ... 2012 Symposium on VLSI Technology (VLSIT), 41-42, 2012 | 62 | 2012 |
| A scalable multi-TeraOPS deep learning processor core for AI trainina and inference B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... 2018 IEEE Symposium on VLSI Circuits, 35-36, 2018 | 61 | 2018 |
| Increasing effective transistor width in memory arrays with dual bitlines GW Burr, K Gopalakrishnan US Patent 7,920,406, 2011 | 60 | 2011 |
