| You cannot improve what you do not measure: FPGA vs. ASIC efficiency gaps for convolutional neural network inference A Boutros, S Yazdanshenas, V Betz ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018 | 79 | 2018 |
| Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs A Boutros, S Yazdanshenas, V Betz International Conference on Field Programmable Logic and Applications (FPL …, 2018 | 62 | 2018 |
| Coding last level STT-RAM cache for high endurance and low power S Yazdanshenas, MR Pirbasti, M Fazeli, A Patooghy IEEE computer architecture letters 13 (2), 73-76, 2013 | 56 | 2013 |
| COFFE 2: Automatic modelling and optimization of complex and heterogeneous FPGA architectures S Yazdanshenas, V Betz ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (1), 1-27, 2019 | 45 | 2019 |
| Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration S Yazdanshenas, K Tatsumura, V Betz Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 37 | 2017 |
| Interconnect Solutions for Virtualized Field-Programmable Gate Arrays S Yazdanshenas, V Betz IEEE Access 6, 10497-10507, 2018 | 31 | 2018 |
| FPGA Logic Block Architectures for Efficient Deep Learning Inference M Eldafrawy, A Boutros, S Yazdanshenas, V Betz ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (3), 1-34, 2020 | 29 | 2020 |
| Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs A Boutros, M Eldafrawy, S Yazdanshenas, V Betz Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 25 | 2019 |
| The Costs of Confidentiality in Virtualized FPGAs S Yazdanshenas, V Betz IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (10 …, 2019 | 24 | 2019 |
| Quantifying and mitigating the costs of FPGA virtualization S Yazdanshenas, V Betz Field Programmable Logic and Applications (FPL), 2017 27th International …, 2017 | 23 | 2017 |
| High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs K Tatsumura, S Yazdanshenas, V Betz 2016 International Conference on Field-Programmable Technology (FPT), 4-11, 2016 | 19 | 2016 |
| Automatic circuit design and modelling for heterogeneous FPGAs S Yazdanshenas, V Betz 2017 International Conference on Field Programmable Technology (ICFPT), 9-16, 2017 | 18 | 2017 |
| Improving Confidentiality in Virtualized FPGAs S Yazdanshenas, V Betz 2018 International Conference on Field-Programmable Technology (FPT), 258-261, 2018 | 11 | 2018 |
| Fine-grained architecture in dark silicon era for SRAM-based reconfigurable devices S Yazdanshenas, H Asadi IEEE Transactions on Circuits and Systems II: Express Briefs 61 (10), 798-802, 2014 | 10 | 2014 |
| Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs K Tatsumura, S Yazdanshenas, V Betz ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (1), 6, 2018 | 8 | 2018 |
| Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays S Yazdanshenas, B Khaleghi, P Ienne, H Asadi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (12 …, 2016 | 5 | 2016 |
| A scalable dependability scheme for routing fabric of SRAM-based reconfigurable devices S Yazdanshenas, H Asadi, B Khaleghi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014 | 5 | 2014 |
| Datacenter-optimized FPGAs S Yazdanshenas University of Toronto (Canada), 2019 | 3 | 2019 |
| Efficient logic blocks architectures for dense mapping of multipliers S Yazdanshenas, T Vanderhoek US Patent 11,768,661, 2023 | | 2023 |
| Freeze And Clear Logic Circuits And Methods For Integrated Circuits S Yazdanshenas, J Chromczak US Patent App. 17/703,974, 2022 | | 2022 |
Vaughn BetzUniversity of TorontoVerified email at eecg.utoronto.ca
