Siddharth Garg

Citée par

	Toutes	Depuis 2019
Citations	9247	7701
indice h	40	34
indice i10	105	80

2000

1000

500

1500

20102011201220132014201520162017201820192020202120222023202428 24 45 83 121 205 272 304 380 504 828 1141 1419 1947 1857

Accès public

Tout afficher

63 articles

10 articles

disponibles

non disponibles

Sur la base des exigences liées au financement

Coauteurs

Ramesh Karri కర్రి రమేష్Professor of Electrical and Computer Engineering, New York UniversityAdresse e-mail validée de nyu.edu
Diana MarculescuThe University of Texas at AustinAdresse e-mail validée de utexas.edu
Jeff J. ZHANGArizona State UniversityAdresse e-mail validée de seas.harvard.edu
Muhammad ShafiqueProfessor, ECE, New York University (AD-UAE, Tandon-USA), Director eBRAIN LabAdresse e-mail validée de nyu.edu
Mahesh TripunitaraProfessor, University of WaterlooAdresse e-mail validée de uwaterloo.ca
Elza ErkipNew York UniversityAdresse e-mail validée de nyu.edu
Jörg HenkelProfessor of Computer Science, Karlsruhe Institute of TechnologyAdresse e-mail validée de kit.edu
Yatish TurakhiaAssistant Professor, University of California, San DiegoAdresse e-mail validée de ucsd.edu
Da-Cheng JuanGoogle Research, National Tsing Hua University, Carnegie Mellon UniversityAdresse e-mail validée de dacheng.info
Jeyavijayan (JV) RajendranAssociate Professor of Electrical and Computer Engineering, Texas A&M UniversityAdresse e-mail validée de tamu.edu
Frank ImesonPhd Graduate, University of WaterlooAdresse e-mail validée de uwaterloo.ca
Radu MarculescuThe University of Texas at AustinAdresse e-mail validée de utexas.edu
Umit Yusuf OgrasGene Amdahl Professor, University of Wisconsin-MadisonAdresse e-mail validée de wisc.edu
Shreyas SundaramMarie Gordon Professor of Electrical and Computer Engineering, Purdue UniversityAdresse e-mail validée de purdue.edu
Catherine RosenbergUniversity of WaterlooAdresse e-mail validée de ece.uwaterloo.ca
Dariush FooladivandaPostdoctoral Fellow, UC BerkeleyAdresse e-mail validée de berkeley.edu
Ashish R. HotaAssistant Professor, Indian Institute of Technology (IIT), KharagpurAdresse e-mail validée de ee.iitkgp.ac.in
Chirag RavishankarSoftware Engineer, XilinxAdresse e-mail validée de xilinx.com
Tulika MitraProfessor of Computer Science, National University of SingaporeAdresse e-mail validée de comp.nus.edu.sg
Farinaz KoushanfarProfessor and Siavouche Nemat-Nasser Endowed Chair of ECE, UC San DiegoAdresse e-mail validée de ucsd.edu

Suivre

Siddharth Garg

New York University

Adresse e-mail validée de nyu.edu - Page d'accueil

ML computer security computer hardware


Titre Trier par citations Trier par année Trier par titre	Citée par Citée par	Année
Badnets: Identifying vulnerabilities in the machine learning model supply chain T Gu, B Dolan-Gavitt, S Garg arXiv preprint arXiv:1708.06733, 2017	1799	2017
Fine-pruning: Defending against backdooring attacks on deep neural networks K Liu, B Dolan-Gavitt, S Garg International Symposium on Research in Attacks, Intrusions, and Defenses …, 2018	1119	2018
Badnets: Evaluating backdooring attacks on deep neural networks T Gu, K Liu, B Dolan-Gavitt, S Garg IEEE Access 7, 47230-47244, 2019	1054	2019
Securing computer hardware using 3d integrated circuit ({IC}) technology and split manufacturing for obfuscation F Imeson, A Emtenan, S Garg, M Tripunitara 22nd {USENIX} Security Symposium ({USENIX} Security 13), 495-510, 2013	261	2013
The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives M Shafique, S Garg, J Henkel, D Marculescu Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014	239	2014
Integrated circuit (IC) decamouflaging: Reverse engineering camouflaged ICs within minutes. M El Massad, S Garg, MV Tripunitara NDSS, 1-14, 2015	235	2015
Safetynets: Verifiable execution of deep neural networks on an untrusted cloud Z Ghodsi, T Gu, S Garg Advances in Neural Information Processing Systems 30, 2017	195	2017
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators J Zhang, K Rangineni, Z Ghodsi, S Garg Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018	170	2018
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator JJ Zhang, T Gu, K Basu, S Garg 2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018	161	2018
Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors B Raghunathan, Y Turakhia, S Garg, D Marculescu 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 39-44, 2013	143	2013
Benchmarking large language models for automated verilog rtl code generation S Thakur, B Ahmad, Z Fan, H Pearce, B Tan, R Karri, B Dolan-Gavitt, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023	138*	2023
Lost at c: A user study on the security implications of large language model code assistants G Sandoval, H Pearce, T Nys, R Karri, S Garg, B Dolan-Gavitt 32nd USENIX Security Symposium (USENIX Security 23), 2205-2222, 2023	122*	2023
Reverse engineering camouflaged sequential circuits without scan access M El Massad, S Garg, M Tripunitara 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 33-40, 2017	116	2017
Securing hardware accelerators: A new challenge for high-level synthesis C Pilato, S Garg, K Wu, R Karri, F Regazzoni IEEE Embedded Systems Letters 10 (3), 77-80, 2017	93	2017
Verifiable asics RS Wahby, M Howald, S Garg, A Shelat, M Walfish 2016 IEEE Symposium on Security and Privacy (SP), 759-778, 2016	93*	2016
Chip-chat: Challenges and opportunities in conversational hardware design J Blocklove, S Garg, R Karri, H Pearce 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 1-6, 2023	92	2023
Deepreduce: Relu reduction for fast private inference NK Jha, Z Ghodsi, S Garg, B Reagen International Conference on Machine Learning, 4839-4849, 2021	91	2021
Cryptonas: Private inference on a relu budget Z Ghodsi, AK Veldanda, B Reagen, S Garg Advances in Neural Information Processing Systems 33, 16961-16971, 2020	90	2020
HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors Y Turakhia, B Raghunathan, S Garg, D Marculescu Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013	79	2013
Nnoculation: Catching badnets in the wild AK Veldanda, K Liu, B Tan, P Krishnamurthy, F Khorrami, R Karri, ... Proceedings of the 14th ACM Workshop on Artificial Intelligence and Security …, 2021	78*	2021

Le système ne peut pas réaliser cette opération maintenant. Veuillez réessayer plus tard.

Articles 1–20

Nombre de citations par an

Citations en double

Citations fusionnées

Ajouter les coauteursCoauteurs

Suivre

Citée par

Coauteurs