Ioannis Koltsidas
Title
Cited by
Cited by
Year
Flashing up the storage layer
I Koltsidas, SD Viglas
Proceedings of the VLDB Endowment 1 (1), 514-525, 2008
2082008
Implementation and implications of a stealth hard-drive backdoor
J Zaddach, A Kurmus, D Balzarotti, EO Blass, A Francillon, T Goodspeed, ...
Proceedings of the 29th annual computer security applications conference …, 2013
802013
Data management over flash memory
I Koltsidas, SD Viglas
Proceedings of the 2011 ACM SIGMOD International Conference on Management of …, 2011
442011
Error correction architecture to increase speed and relax current drive requirements of SAR ADC
C Srinivasan, KM Godbole
US Patent 6,747,589, 2004
412004
Crail: A High-Performance I/O Architecture for Distributed Data Processing.
P Stuedi, A Trivedi, J Pfefferle, R Stoica, B Metzler, N Ioannou, I Koltsidas
IEEE Data Eng. Bull. 40 (1), 38-49, 2017
392017
GPFS-SNC: An enterprise storage framework for virtual-machine clouds
K Gupta, R Jain, I Koltsidas, H Pucha, P Sarkar, M Seaman, D Subhraveti
IBM Journal of Research and Development 55 (6), 2: 1-2: 10, 2011
382011
Vertical sub-micron CMOS transistors on (110),(111),(311),(511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same
L Forbes, W Noble, A Reinberg
US Patent App. 10/222,997, 2004
332004
On the [ir] relevance of network performance for data processing
A Trivedi, P Stuedi, J Pfefferle, R Stoica, B Metzler, I Koltsidas, N Ioannou
8th {USENIX} Workshop on Hot Topics in Cloud Computing (HotCloud 16), 2016
272016
Write cache structure in a storage system
I Koltsidas, R Pletka
US Patent 8,990,502, 2015
272015
XArch: archiving scientific and reference data
H Müller, P Buneman, I Koltsidas
Proceedings of the 2008 ACM SIGMOD international conference on Management of …, 2008
272008
Multi-lug socket tool
L Boston
US Patent 6,668,685, 2003
27*2003
Reaping the performance of fast {NVM} storage with uDepot
K Kourtis, N Ioannou, I Koltsidas
17th {USENIX} Conference on File and Storage Technologies ({FAST} 19), 1-15, 2019
252019
Dynamically adjusted threshold for population of secondary cache
MT Benhase, SL Blinick, ES Eleftheriou, LM Gupta, R Haas, XY Hu, ...
US Patent 8,972,661, 2015
252015
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
222018
Two-level hierarchical log structured array architecture with minimized write amplification
R Haas, N Ioannou, I Koltsidas, RA Pletka, AD Walls
US Patent 9,619,158, 2017
222017
Extending useful life of a non-volatile memory by health grading
CJ Camp, I Koltsidas, N Papandreou, T Parnell, RA Pletka, C Pozidis, ...
US Patent 9,558,107, 2017
222017
Reading files stored on a storage system
ES Eleftheriou, R Haas, N Haustein, J Jelitto, I Koltsidas, S Sarafijanovic, ...
US Patent 8,862,815, 2014
212014
Management of partial data segments in dual cache systems
MT Benhase, SL Blinick, ES Eleftheriou, LM Gupta, R Haas, XY Hu, ...
US Patent 8,688,913, 2014
192014
Cache allocation in a computerized system
XY Hu, N Ioannou, I Koltsidas
US Patent 9,342,458, 2016
182016
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
182016
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