| FPGA implementation of a LDPC decoder using a reduced complexity message passing algorithm VA Chandrasetty, SM Aziz Journal of Networks 6 (1), 36-45, 2011 | 53 | 2011 |
| FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm VA Chandrasetty, SM Aziz Computer Research and Development, 2010 Second International Conference on …, 2010 | 48 | 2010 |
| An area efficient LDPC decoder using a reduced complexity min-sum algorithm VA Chandrasetty, SM Aziz Integration, the VLSI Journal 45 (2), 141-148, 2012 | 44 | 2012 |
| Resource efficient LDPC decoders for multimedia communication VA Chandrasetty, SM Aziz INTEGRATION, the VLSI journal 48, 213-220, 2015 | 29 | 2015 |
| VLSI Design: A Practical Guide for FPGA and ASIC Implementations VA Chandrasetty Springer Verlag, 2011 | 27* | 2011 |
| Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes VA Chandrasetty, SJ Johnson, G Lechner IET Communications 8 (17), 3179-3188, 2014 | 26* | 2014 |
| A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation VA Chandrasetty, SM Aziz Journal of Networks 7 (3), 441-449, 2012 | 18 | 2012 |
| A reduced complexity message passing algorithm with improved performance for LDPC decoding VA Chandrasetty, SM Aziz Computers and Information Technology, 2009. ICCIT'09. 12th International …, 2009 | 12 | 2009 |
| A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders VA Chandrasetty, SM Aziz Multimedia and Expo (ICME), 2011 IEEE International Conference on, 1-7, 2011 | 11 | 2011 |
| Analysis of performance and implementation complexity of simplified algorithms for decoding low-density parity-check codes VA Chandrasetty, SM Aziz GLOBECOM Workshops (GC Wkshps), 2010 IEEE, 430-435, 2010 | 8 | 2010 |
| A novel dual processing architecture for implementation of motion estimation unit of H. 264 AVC on FPGA VA Chandrasetty, SR Laddha Industrial Electronics & Applications, 2009. ISIEA 2009. IEEE Symposium on 1 …, 2009 | 5 | 2009 |
| Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders VA Chandrasetty, SM Aziz Computer and Information Technology (ICCIT), 2010 13th International …, 2010 | 4 | 2010 |
| Resource efficient flexible architectures for low-density parity-check decoders VA Chandrasetty | | 2012 |
| High performance error correction codes for communication systems: research proposal VA Chandrasetty | | |
Syed Mahfuzul AzizProfessor, Electrical & Electronic Engineering, UniSA STEM, University of South AustraliaVerified email at unisa.edu.au
