| An optimized architecture of HEVC core transform using real-valued DCT coefficients S Chatterjee, K Sarawadekar IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 2052-2056, 2018 | 27 | 2018 |
| WHT and matrix decomposition-based approximated IDCT architecture for HEVC S Chatterjee, K Sarawadekar IEEE Transactions on Circuits and Systems II: Express Briefs 66 (6), 1043-1047, 2018 | 7 | 2018 |
| A low cost, constant throughput and reusable 8# x00D7; 8 DCT architecture for HEVC S Chatterjee, KP Sarawadekar 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | 5 | 2016 |
| Approximated core transform architectures for HEVC using WHT-based decomposition method S Chatterjee, K Sarawadekar IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4296-4308, 2019 | 4 | 2019 |
| Constant throughput HEVC core transform design S Chatterjee, K Sarawadekar 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | 2 | 2016 |
| Exploiting trigonometric properties to optimize higher order DCT architecture in HEVC S Chatterjee, K Sarawadekar IEEE Transactions on Circuits and Systems for Video Technology 30 (10), 3598 …, 2019 | 1 | 2019 |
| Hybrid Beamforming for Secured mmWave MIMO Communication R Pal, G Modanwal, S Chatterjee, KP Sarawadekar Security and Privacy in Cyberspace, 187-207, 2022 | | 2022 |
| VLSI Architectures for the Core Transform in High Efficiency Video Coding S Chatterjee IIT (BHU) varanasi, 2019 | | 2019 |
| A Constant Throughput Integer DCT VLSI Architecture for HEVC S Chatterjee, K Sarawadekar | | |
| VLSI Architectures for the Core Transform in High Efficiency Video Coding S Chatterjee Varanasi, 0 | | |
