Uri Weiser
Uri Weiser
Professor, Technion
Verified email at ee.technion.ac.il - Homepage
Title
Cited by
Cited by
Year
MMX technology extension to the Intel architecture
A Peleg, U Weiser
IEEE micro 16 (4), 42-50, 1996
7521996
TEAM: Threshold adaptive memristor model
S Kvatinsky, EG Friedman, A Kolodny, UC Weiser
IEEE transactions on circuits and systems I: regular papers 60 (1), 211-221, 2012
5462012
Interconnect-power dissipation in a microprocessor
N Magen, A Kolodny, U Weiser, N Shamir
Proceedings of the 2004 international workshop on System level interconnect …, 2004
5142004
Memristor-based material implication (IMPLY) logic: Design principles and methodologies
S Kvatinsky, G Satat, N Wald, EG Friedman, A Kolodny, UC Weiser
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (10 …, 2013
3582013
MAGIC—Memristor-aided logic
S Kvatinsky, D Belousov, S Liman, G Satat, N Wald, EG Friedman, ...
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 895-899, 2014
3542014
Intel MMX for multimedia PCs
A Peleg, S Wilkie, U Weiser
Communications of the ACM 40 (1), 24-38, 1997
2531997
Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
A Peleg, U Weiser
US Patent 5,381,533, 1995
2521995
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
TY Morad, UC Weiser, A Kolodnyt, M Valero, E Ayguade
IEEE Computer Architecture Letters 5 (1), 14-17, 2006
2362006
MRL—Memristor ratioed logic
S Kvatinsky, N Wald, G Satat, A Kolodny, UC Weiser, EG Friedman
2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012
1912012
Correlated load-address predictors
M Bekerman, S Jourdan, R Ronen, G Kirshenboim, L Rappoport, A Yoaz, ...
ACM SIGARCH Computer Architecture News 27 (2), 54-63, 1999
1351999
Many-core vs. many-thread machines: Stay away from the valley
Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser
IEEE Computer Architecture Letters 8 (1), 25-28, 2009
1282009
Memristor-based IMPLY logic design procedure
S Kvatinsky, A Kolodny, UC Weiser, EG Friedman
2011 IEEE 29th International Conference on Computer Design (ICCD), 142-147, 2011
1252011
A wavefront notation tool for VLSI array design
U Weiser, AL Davis
VLSI Systems and Computations, 226-234, 1981
1091981
Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
UC Weiser, D Perlmutter, Y Yaari
US Patent 5,265,213, 1993
891993
Branch prediction and resolution apparatus for a superscalar computer processor
ET Grochowski, DB Alpert, JD Mills, UC Weiser
US Patent 5,442,756, 1995
781995
VLSI systems and computations
HT Kung, R Sproull, G Steele
Springer Science & Business Media, 2012
762012
Branch prediction and resolution apparatus for a superscalar computer processor
ET Grochowski, DB Alpert, JD Mills, UC Weiser
US Patent 5,606,676, 1997
711997
Towards a formal treatment of VLSI arrays
L Johnsson, U Weiser, D Cohen, AL Davis
California Institute of Technology, 1981
691981
Hamiltonian neural networks
S Greydanus, M Dzamba, J Yosinski
Advances in Neural Information Processing Systems, 15379-15389, 2019
672019
The desired memristor for circuit designers
S Kvatinsky, EG Friedman, A Kolodny, UC Weiser
IEEE Circuits and Systems Magazine 13 (2), 17-22, 2013
652013
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