Rudy Lauwereins
Rudy Lauwereins
Vice president imec and professor computer architectures, KU Leuven, Belgium
Verified email at imec.be
Title
Cited by
Cited by
Year
Cycle-static dataflow
G Bilsen, M Engels, R Lauwereins, J Peperstraete
IEEE Transactions on signal processing 44 (2), 397-408, 1996
8291996
ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
International Conference on Field Programmable Logic and Applications, 61-70, 2003
7082003
Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs
T Marescaux, A Bartic, D Verkest, S Vernalde, R Lauwereins
International Conference on Field Programmable Logic and Applications, 795-805, 2002
2652002
Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
IEE Proceedings-Computers and Digital Techniques 150 (5), 255-261, 2003
2622003
DRESC: A retargetable compiler for coarse-grained reconfigurable architectures
B Mei, S Vernalde, D Verkest, H De Man, R Lauwereins
2002 IEEE International Conference on Field-Programmable Technology, 2002 …, 2002
2432002
Architecture exploration for a reconfigurable architecture template
B Mei, A Lambrechts, JY Mignolet, D Verkest, R Lauwereins
IEEE Design & Test of Computers 22 (2), 90-101, 2005
2212005
Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip
JY Mignolet, V Nollet, P Coene, D Verkest, S Vernalde, R Lauwereins
2003 Design, Automation and Test in Europe Conference and Exhibition, 986-991, 2003
1932003
Energy-aware runtime scheduling for embedded-multiprocessor SOCs
P Yang, C Wong, P Marchal, F Catthoor, D Desmet, D Verkest, ...
IEEE Design & Test of Computers 18 (05), 46-58, 2001
1912001
Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: A case study
B Mei, S Vernalde, D Verkest, R Lauwereins
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
1872004
Grape-II: A system-level prototyping environment for DSP applications
R Lauwereins, M Engels, M Ade, JA Peperstraete
Computer 28 (2), 35-43, 1995
1841995
Designing an operating system for a heterogeneous reconfigurable SoC
V Nollet, P Coene, D Verkest, S Vernalde, R Lauwereins
Proceedings International Parallel and Distributed Processing Symposium, 7 pp., 2003
1492003
Reconfigurable instruction set processors from a hardware/software perspective
F Barat, R Lauwereins, G Deconinck
IEEE Transactions on Software Engineering 28 (9), 847-862, 2002
1282002
Networks on chip as hardware components of an OS for reconfigurable systems
T Marescaux, JY Mignolet, A Bartic, W Moffat, D Verkest, S Vernalde, ...
International Conference on Field Programmable Logic and Applications, 595-605, 2003
1252003
Topology adaptive network-on-chip design and implementation
TA Bartic, JY Mignolet, V Nollet, T Marescaux, D Verkest, S Vernalde, ...
IEE Proceedings-Computers and Digital Techniques 152 (4), 467-472, 2005
1102005
Managing dynamic concurrent tasks in embedded real-time multimedia systems
P Yang, P Marchal, C Wong, S Himpe, F Catthoor, P David, J Vounckx, ...
Proceedings of the 15th international symposium on System Synthesis, 112-119, 2002
1032002
Grape: A CASE tool for digital signal parallel processing
R Lauwereins, M Engels, J Peperstraete, E Steegmans, ...
IEEE ASSP Magazine 7 (2), 32-43, 1990
991990
Reconfigurable instruction set processors: a survey
F Barat, R Lauwereins
Proceedings 11th International Workshop on Rapid System Prototyping. RSP …, 2000
982000
A scalable 8.7 nJ/bit 75.6 Mb/s parallel concatenated convolutional (turbo-) codec
B Bougard, A Giulietti, V Derudder, JW Weijers, S Dupont, L Hollevoet, ...
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of …, 2003
902003
Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets
M Adé, R Lauwereins, JA Peperstraete
Proceedings of the 34th annual design automation conference, 64-69, 1997
891997
Highly scalable network on chip for reconfigurable systems
TA Bartic, JY Mignolet, V Nollet, T Marescaux, D Verkest, S Vernalde, ...
Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No …, 2003
872003
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