Thomas B.  Preußer
Thomas B. Preußer
Accemic Technologies
Verified email at - Homepage
Cited by
Cited by
FINN-R An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
M Blott, TB Preußer, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018
The embedded Java benchmark suite JemBench
M Schoeberl, TB Preusser, S Uhrig
Proceedings of the 8th International Workshop on Java Technologies for Real …, 2010
Secure, real-time and multi-threaded general-purpose embedded Java microarchitecture
M Zabel, TB Preußer, P Reichel, RG Spallek
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
Next-generation massively parallel short-read mapping on FPGAs
O Knodel, TB Preußer, RG Spallek
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
Bump-pointer method caching for embedded Java processors
TB Preusser, M Zabel, RG Spallek
Proceedings of the 5th international workshop on Java technologies for real …, 2007
Short-read mapping by a systolic custom FPGA computation
TB Preußer, O Knodel, RG Spallek
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
FPGA-specific arithmetic optimizations of short-latency adders
HD Nguyen, B Pasca, TB Preußer
2011 21st International Conference on Field Programmable Logic and …, 2011
Inference of quantized neural networks on heterogeneous all-programmable devices
TB Preußer, G Gambardella, N Fraser, M Blott
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 833-838, 2018
Mapping basic prefix computations to fast carry-chain structures
TB Preußer, RG Spallek
2009 International Conference on Field Programmable Logic and Applications …, 2009
The SHAP microarchitecture and Java virtual machine
TB Preußer, M Zabel, P Reichel
Enhancing FPGA device capabilities by the automatic logic mapping to additive carry chains
TB Preußer, RG Spallek
2010 International Conference on Field Programmable Logic and Applications …, 2010
Accelerating computations on FPGA carry chains by operand compaction
TB Preußer, M Zabel, RG Spallek
2011 IEEE 20th Symposium on Computer Arithmetic, 95-102, 2011
Putting queens in carry chains
TB Preußer, B Nägel, RG Spallek
Ready PCIe data streaming solutions for FPGAs
TB Preußer, RG Spallek
2014 24th International Conference on Field Programmable Logic and …, 2014
Design space exploration of coarse-grain reconfigurable dsps
M Zabel, S Kohler, M Zimmerling, TB Preuber, RG Spallek
2005 International Conference on Reconfigurable Computing and FPGAs …, 2005
Putting Queens in Carry Chains, N o 27
TB Preußer, MR Engelhardt
Journal of Signal Processing Systems 88 (2), 185-201, 2017
Scaling neural network performance through customized hardware architectures on reconfigurable logic
M Blott, TB Preußer, N Fraser, G Gambardella, K O'Brien, Y Umuroglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 419-422, 2017
Weasel: A platform-independent streaming-optimized sata controller
P Lehmann, T Frank, O Knodel, S Köhler, TB Preußer, RG Spallek
2013 23rd International Conference on Field programmable Logic and …, 2013
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
TB Preußer
2017 27th International Conference on Field Programmable Logic and …, 2017
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC
P Russell, J Döge, C Hoppe, TB Preußer, P Reichel, P Schneider
2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017
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