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Thomas B.  Preußer
Thomas B. Preußer
Xilinx Research
Verified email at utexas.edu - Homepage
Title
Cited by
Cited by
Year
FINN-R An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
M Blott, TB Preußer, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018
1992018
The embedded Java benchmark suite JemBench
M Schoeberl, TB Preusser, S Uhrig
Proceedings of the 8th International Workshop on Java Technologies for Real …, 2010
562010
Next-generation massively parallel short-read mapping on FPGAs
O Knodel, TB Preußer, RG Spallek
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
492011
Secure, real-time and multi-threaded general-purpose embedded Java microarchitecture
M Zabel, TB Preußer, P Reichel, RG Spallek
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
472007
Inference of quantized neural networks on heterogeneous all-programmable devices
TB Preußer, G Gambardella, N Fraser, M Blott
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 833-838, 2018
322018
Short-read mapping by a systolic custom FPGA computation
TB Preußer, O Knodel, RG Spallek
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
292012
FPGA-specific arithmetic optimizations of short-latency adders
HD Nguyen, B Pasca, TB Preußer
2011 21st International Conference on Field Programmable Logic and …, 2011
282011
Bump-pointer method caching for embedded Java processors
TB Preusser, M Zabel, RG Spallek
Proceedings of the 5th international workshop on Java technologies for real …, 2007
262007
Accelerating computations on FPGA carry chains by operand compaction
TB Preußer, M Zabel, RG Spallek
2011 IEEE 20th Symposium on Computer Arithmetic, 95-102, 2011
232011
Enhancing FPGA device capabilities by the automatic logic mapping to additive carry chains
TB Preußer, RG Spallek
2010 International Conference on Field Programmable Logic and Applications …, 2010
232010
Mapping basic prefix computations to fast carry-chain structures
TB Preußer, RG Spallek
2009 International Conference on Field Programmable Logic and Applications …, 2009
212009
The SHAP microarchitecture and Java virtual machine
TB Preußer, M Zabel, P Reichel
212007
Putting queens in carry chains
TB Preußer, B Nägel, RG Spallek
Techn. Univ., Fak. Informatik, 2009
172009
Ready PCIe data streaming solutions for FPGAs
TB Preußer, RG Spallek
2014 24th International Conference on Field Programmable Logic and …, 2014
152014
Optimizing bit-serial matrix multiplication for reconfigurable computing
Y Umuroglu, D Conficconi, L Rasnayake, TB Preusser, M Själander
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (3), 1-24, 2019
132019
Putting queens in carry chains, n o̱27
TB Preußer, MR Engelhardt
Journal of Signal Processing Systems 88 (2), 185-201, 2017
132017
Design space exploration of coarse-grain reconfigurable dsps
M Zabel, S Kohler, M Zimmerling, TB Preuber, RG Spallek
2005 International Conference on Reconfigurable Computing and FPGAs …, 2005
132005
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
TB Preußer
2017 27th International Conference on Field Programmable Logic and …, 2017
122017
Scaling neural network performance through customized hardware architectures on reconfigurable logic
M Blott, TB Preußer, N Fraser, G Gambardella, K O'Brien, Y Umuroglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 419-422, 2017
102017
Solving Sudokus through an Incidence Matrix on an FPGA
M Dittrich, TB Preußer, RG Spallek
2010 International Conference on Field-Programmable Technology, 465-469, 2010
92010
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