Abhisek Dixit
Abhisek Dixit
Associate Professor of Electrical Engineering, IIT Delhi, New Delhi, India
Verified email at ee.iitd.ac.in - Homepage
Cited by
Cited by
Analysis of the parasitic S/D resistance in multiple-gate FETs
A Dixit, A Kottantharayil, N Collaert, M Goodwin, M Jurczak, K De Meyer
IEEE Transactions on Electron Devices 52 (6), 1132-1140, 2005
Multiple gate semiconductor device and method for forming same
A Dixit, K De Meyer
US Patent 7,202,517, 2007
Impact of line-edge roughness on FinFET matching performance
E Baravelli, A Dixit, R Rooyackers, M Jurczak, N Speciale, K De Meyer
IEEE Transactions on Electron Devices 54 (9), 2466-2474, 2007
Multi-gate devices for the 32 nm technology node and beyond
N Collaert, A De Keersgieter, A Dixit, I Ferain, LS Lai, D Lenoble, ...
Solid-State Electronics 52 (9), 1291-1296, 2008
FinFET analogue characterization from DC to 110 GHz
D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ...
Solid-State Electronics 49 (9), 1488-1496, 2005
Impact of LER and random dopant fluctuations on FinFET matching performance
E Baravelli, M Jurczak, N Speciale, K De Meyer, A Dixit
IEEE transactions on nanotechnology 7 (3), 291-298, 2008
A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node
N Collaert, A Dixit, M Goodwin, KG Anil, R Rooyackers, B Degroote, ...
IEEE Electron Device Letters 25 (8), 568-570, 2004
A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM
K Von Arnim, E Augendre, C Pacha, T Schulz, KT San, F Bauer, ...
2007 IEEE Symposium on VLSI Technology, 106-107, 2007
25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/in the source and drain regions
P Verheyen, N Collaert, R Rooyackers, R Loo, D Shamiryan, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 194-195, 2005
Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness
A Dixit, KG Anil, E Baravelli, P Roussel, A Mercha, C Gustin, M Bamal, ...
2006 International Electron Devices Meeting, 1-4, 2006
Reliability comparison of triple-gate versus planar SOI FETs
F Crupi, B Kaczer, R Degraeve, V Subramanian, P Srinivasan, E Simoen, ...
IEEE Transactions on electron devices 53 (9), 2351-2357, 2006
GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices
T Hoffmann, G Doornbos, I Ferain, N Collaert, P Zimmerman, M Goodwin, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
B Degroote, R Rooyackers, T Vandeweyer, N Collaert, W Boullart, ...
Microelectronic engineering 84 (4), 609-618, 2007
High density six transistor FinFET SRAM cell layout
A Dixit
US Patent 8,445,384, 2013
Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions
A Dixit, KG Anil, R Rooyackers, F Leys, M Kaiser, N Collaert, K De Meyer, ...
Solid-state electronics 50 (4), 587-593, 2006
Multi-gate devices for the 32 nm technology node and beyond: Challenges for selective epitaxial growth
N Collaert, R Rooyackers, A Hikavyy, A Dixit, F Leys, P Verheyen, R Loo, ...
Thin Solid Films 517 (1), 101-104, 2008
Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET
R Singh, K Aditya, SS Parihar, YS Chauhan, R Vega, TB Hook, A Dixit
IEEE Electron Device Letters 39 (8), 1246-1249, 2018
CMOS inverter device with fin structures
A Dixit
US Patent 8,258,577, 2012
Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency
R Rooyackers, E Augendre, B Degroote, N Collaert, A Nackaerts, A Dixit, ...
2006 International Electron Devices Meeting, 1-4, 2006
A 0.314/spl mu/m/sup 2/6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75 NA 193nm lithography
A Nackaerts, M Ercken, S Demuynck, A Lauwers, C Baerts, H Bender, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
The system can't perform the operation now. Try again later.
Articles 1–20