| Architecting large-scale SRAM arrays with monolithic 3D integration J Kong, YH Gong, SW Chung 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 28 | 2017 |
| Quantifying the impact of monolithic 3D (M3D) integration on L1 caches YH Gong, J Kong, SW Chung IEEE Transactions on Emerging Topics in Computing 9 (2), 854-865, 2019 | 22 | 2019 |
| Exploiting refresh effect of DRAM read operations: A practical approach to low-power refresh YH Gong, SW Chung IEEE Transactions on Computers 65 (5), 1507-1517, 2016 | 22 | 2016 |
| Thermal Modeling and Validation of a Real-World Mobile AP YH Gong, JJ Yoo, SW Chung IEEE Design & Test 35 (1), 55-62, 2018 | 21 | 2018 |
| Monolithic 3D-based SRAM/MRAM Hybrid Memory for an Energy-efficient Unified L2 TLB-Cache Architecture YH Gong IEEE Access 9, 18915-18926, 2021 | 7 | 2021 |
| Hybrid memory system and refresh method thereof based on a read-to-write ratio of a page SW Chung, YH GONG, JH Chung, HH CHO US Patent App. 10/198,211, 2019 | 7* | 2019 |
| Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme J Kong, YH Gong, SW Chung Microprocessors and Microsystems 49, 95-104, 2017 | 7 | 2017 |
| Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks YS Lee, EY Chung, YH Gong, SW Chung IEEE Embedded Systems Letters 13 (4), 162-165, 2021 | 5 | 2021 |
| Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency CT Do, YH Gong, CH Kim, SW Kim, SW Chung 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 5 | 2019 |
| A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM JH Choi, YH Gong, SW Chung Electronics 10 (5), 623, 2021 | 4 | 2021 |
| Monolithic 3D stacked multiply-accumulate units YS Lee, KM Kim, JH Lee, YH Gong, SW Kim, SW Chung Integration 76, 183-189, 2021 | 4 | 2021 |
| Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches YH Gong, JM Kim, SK Lim, SW Chung Microprocessors and Microsystems 42, 100-112, 2016 | 4 | 2016 |
| Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience YS Lee, G Koo, YH Gong, SW Chung 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 382-387, 2022 | 3 | 2022 |
| Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors JH Lee, YS Lee, JH Choi, H Amrouch, J Kong, YH Gong, SW Chung IEEE Access 9, 120715-120729, 2021 | 2 | 2021 |
| Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay YH Gong, HB Jang, SW Chung International Symposium on Quality Electronic Design (ISQED), 524-530, 2013 | 2 | 2013 |
| Scale-CIM: Precision-scalable computing-in-memory for energy-efficient quantized neural networks YS Lee, YH Gong, SW Chung Journal of Systems Architecture 134, 102787, 2023 | 1 | 2023 |
| An efficient trade-off between yield and energy for eDRAM caches under process variations J Kong, YH Gong Microprocessors and Microsystems 55, 1-12, 2017 | 1 | 2017 |
| Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory J Hong, S Cho, G Park, W Yang, YH Gong, G Kim 2024 IEEE International Symposium on High-Performance Computer Architecture …, 2024 | | 2024 |
| HedgeRank: Heterogeneity-Aware, Energy-Efficient Partitioning of Personalized PageRank at the Edge YH Gong Micromachines 14 (9), 1714, 2023 | | 2023 |
| Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience HK Bae, MJ Chung, YH Gong, SW Chung 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | | 2023 |
Sung Woo Chungkorea universityVerified email at korea.ac.kr
