Arun Raghavan
Arun Raghavan
Oracle Labs
Verified email at - Homepage
Cited by
Cited by
Computational sprinting
A Raghavan, Y Luo, A Chandawalla, M Papaefthymiou, KP Pipe, ...
IEEE international symposium on high-performance comp architecture, 1-12, 2012
Rethinking SIMD vectorization for in-memory databases
O Polychroniou, A Raghavan, KA Ross
Proceedings of the 2015 ACM SIGMOD International Conference on Management of …, 2015
TRANSIT: specifying protocols with concolic snippets
A Udupa, A Raghavan, JV Deshmukh, S Mador-Haim, MMK Martin, R Alur
ACM SIGPLAN Notices 48 (6), 287-296, 2013
Computational sprinting on a hardware/software testbed
A Raghavan, L Emurian, L Shao, M Papaefthymiou, KP Pipe, TF Wenisch, ...
ACM SIGARCH Computer Architecture News 41 (1), 155-166, 2013
Token tenure: PATCHing token counting using directory-based cache coherence
A Raghavan, C Blundell, MMK Martin
2008 41st IEEE/ACM International Symposium on Microarchitecture, 47-58, 2008
Figure-of-merit for phase-change materials used in thermal management
L Shao, A Raghavan, GH Kim, L Emurian, J Rosen, MC Papaefthymiou, ...
International Journal of Heat and Mass Transfer 101, 764-771, 2016
RETCON: transactional repair without replay
C Blundell, A Raghavan, MMK Martin
ACM SIGARCH Computer Architecture News 38 (3), 258-269, 2010
A many-core architecture for in-memory data processing
SR Agrawal, S Idicula, A Raghavan, E Vlachos, V Govindaraju, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
Utilizing dark silicon to save energy with computational sprinting
A Raghavan, L Emurian, L Shao, M Papaefthymiou, KP Pipe, TF Wenisch, ...
Ieee Micro 33 (5), 20-28, 2013
On-chip phase change heat sinks designed for computational sprinting
L Shao, A Raghavan, L Emurian, MC Papaefthymiou, TF Wenisch, ...
2014 Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM …, 2014
Hybrid instrumentation framework for multicore low power processors
S Idicula, K Kashyap, A Raghavan, E Vlachos, V Govindaraju
US Patent 10,503,626, 2019
Designing for responsiveness with computational sprinting
A Raghavan, Y Luo, A Chandawalla, M Papaefthymiou, KP Pipe, ...
Ieee Micro 33 (3), 8-15, 2013
Rapid: In-memory analytical query processing engine with extreme performance per watt
C Balkesen, N Kunal, G Giannikis, P Fender, S Sundara, F Schmidt, ...
Proceedings of the 2018 International Conference on Management of Data, 1407 …, 2018
Pitfalls of accurately benchmarking thermally adaptive chips
L Emurian, A Raghavan, L Shao, JM Rosen, M Papaefthymiou, K Pipe, ...
Power (W) 5 (10), 2014
Disk drive failure prediction with neural networks
O Kocberber, F Schmidt, A Raghavan, N Agarwal, S Idicula, GT Zhou, ...
US Patent App. 16/144,912, 2020
Token tenure and PATCH: a predictive/adaptive Token-counting hybrid
A Raghavan, C Blundell, MMK Martin
ACM Transactions on Architecture and Code Optimization (TACO) 7 (2), 6, 2010
Efficient parallel algorithm for integral image computation for many-core CPUs
V Varadarajan, A Raghavan, S Idicula, N Agarwal
US Patent 10,529,049, 2020
Big data processing: Scalability with extreme single-node performance
V Govindaraju, S Idicula, S Agrawal, V Vardarajan, A Raghavan, J Wen, ...
2017 IEEE International Congress on Big Data (BigData Congress), 129-136, 2017
Computational sprinting: Exceeding sustainable power in thermally constrained systems
A Raghavan
University of Pennsylvania, 2013
Memory coherence in a multi-core, multi-level, heterogeneous computer architecture implementing hardware-managed and software managed caches
A Di Blas, A Basant, A Raghavan, N Agarwal
US Patent 10,417,128, 2019
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