| A 201.4 GOPS 496 mW real-time multi-object recognition processor with bio-inspired neural perception engine JY Kim, M Kim, S Lee, J Oh, K Kim, HJ Yoo IEEE Journal of Solid-State Circuits 45 (1), 32-45, 2009 | 157 | 2009 |
| A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Training and Inference B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... 2018 IEEE Symposium on VLSI Circuits, 35-36, 2018 | 154 | 2018 |
| Approximate computing: Challenges and opportunities A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, JODA Prener, ... Rebooting Computing (ICRC), IEEE International Conference on, 1-8, 2016 | 124 | 2016 |
| A 345 mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition S Lee, J Oh, J Park, J Kwon, M Kim, HJ Yoo IEEE Journal of Solid-State Circuits 46 (1), 42-51, 2010 | 105 | 2010 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 88 | 2021 |
| 9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 85 | 2021 |
| Efficient AI system design with cross-layer approximate computing S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ... Proceedings of the IEEE 108 (12), 2232-2250, 2020 | 57 | 2020 |
| A 1.22 TOPS and 1.52 mW/MHz augmented reality multicore processor with neural network NoC for HMD applications G Kim, K Lee, Y Kim, S Park, I Hong, K Bong, HJ Yoo IEEE Journal of Solid-State Circuits 50 (1), 113-124, 2014 | 49 | 2014 |
| A 3.0 TFLOPS 0.62 V scalable processor core for high compute utilization AI training and inference J Oh, SK Lee, M Kang, M Ziegler, J Silberman, A Agrawal, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 44 | 2020 |
| A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams J Oh, G Kim, J Park, I Hong, S Lee, HJ Yoo 2012 IEEE International Solid-State Circuits Conference, 220-222, 2012 | 40 | 2012 |
| Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits CY Chen, K Gopalakrishnan, J Oh, SK Shukla, V Srinivasan US Patent App. 10/120,685, 2018 | 37 | 2018 |
| Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits CY Chen, K Gopalakrishnan, J Oh, SK Shukla, V Srinivasan US Patent App. 14/932,672, 2015 | 37 | 2015 |
| A scalable multi-TeraOPS core for AI training and inference S Shukla, B Fleischer, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... IEEE Solid-State Circuits Letters 1 (12), 217-220, 2019 | 34 | 2019 |
| Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits CY Chen, K Gopalakrishnan, J Oh, LM Saltzman, SK Shukla, V Srinivasan US Patent App. 14/932,629, 2015 | 33* | 2015 |
| A 118.4 gb/s multi-casting network-on-chip with hierarchical star-ring combined topology for real-time object recognition JY Kim, J Park, S Lee, M Kim, J Oh, HJ Yoo IEEE Journal of Solid-State Circuits 45 (7), 1399-1409, 2010 | 31 | 2010 |
| A 57 mW 12.5 µJ/Epoch embedded mixed-mode neuro-fuzzy processor for mobile real-time object recognition J Oh, G Kim, BG Nam, HJ Yoo IEEE journal of solid-state circuits 48 (11), 2894-2907, 2013 | 29 | 2013 |
| A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams J Oh, G Kim, J Park, I Hong, S Lee, JY Kim, JH Woo, HJ Yoo Solid-State Circuits, IEEE Journal of 48 (1), 33-45, 2013 | 28 | 2013 |
| A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor J Oh, J Park, G Kim, S Lee, HJ Yoo 2011 IEEE International Solid-State Circuits Conference, 130-132, 2011 | 26 | 2011 |
| A 7-nm four-core mixed-precision AI chip with 26.2-TFLOPS hybrid-FP8 training, 104.9-TOPS INT4 inference, and workload-aware throttling SK Lee, A Agrawal, J Silberman, M Ziegler, M Kang, S Venkataramani, ... IEEE Journal of Solid-State Circuits 57 (1), 182-197, 2021 | 23 | 2021 |
| Low-Power Real-Time Object Recognition Processors for Mobile Vision Systems J Oh, G Kim, I Hong, J Park, S Lee, J Kim, J Woo, H Yoo IEEE MICRO 32 (6), 38-50, 2012 | 22 | 2012 |
Joo-Young KimKAISTVerified email at kaist.ac.kr
