| Modeling of charge loss mechanisms during the short term retention operation in 3-D NAND flash memories C Woo, M Lee, S Kim, J Park, GB Choi, M Seo, KH Noh, M Kang, H Shin 2019 Symposium on VLSI Technology, T214-T215, 2019 | 27 | 2019 |
| Analysis of failure mechanisms during the long-term retention operation in 3-D NAND flash memories S Kim, K Lee, C Woo, Y Hwang, H Shin IEEE Transactions on Electron Devices 67 (12), 5472-5478, 2020 | 21 | 2020 |
| Modeling of charge failure mechanisms during the short term retention depending on program/erase cycle counts in 3-D NAND flash memories C Woo, S Kim, J Park, H Shin, H Kim, GB Choi, MS Seo, KH Noh 2020 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2020 | 21 | 2020 |
| Modeling of lateral migration mechanism during the retention operation in 3D NAND flash memories C Woo, S Kim, J Park, D Lee, M Kang, J Jeon, H Shin 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 261-263, 2019 | 14 | 2019 |
| Separation of lateral migration components by hole during the short-term retention operation in 3-D NAND flash memories S Kim, H Kim, C Woo, GB Choi, MS Seo, H Shim, KH Noh, H Shin IEEE Transactions on Electron Devices 67 (6), 2645-2647, 2020 | 11 | 2020 |
| Effect of device scaling on lateral migration mechanism of electrons in V-NAND C Woo, S Kim, J Park, H Shin 2019 Silicon Nanoelectronics Workshop (SNW), 1-2, 2019 | 8 | 2019 |
| Cell pattern dependency of charge failure mechanisms during short-term retention in 3-D NAND flash memories C Woo, S Kim, H Shin IEEE Electron Device Letters 41 (11), 1645-1648, 2020 | 7 | 2020 |
| Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices K Ko, C Woo, M Kim, Y Seo, S Kim, M Kang, H Shin JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17 (5), 691-696, 2017 | 3 | 2017 |
| Line Edge Roughness and Process Variation Effect of Three Stacked Gate-All-Around Silicon MOSFET Devices D Son, K Ko, C Woo, M Kang, H Shin Journal of Nanoscience and Nanotechnology 17 (10), 7130-7133, 2017 | 3 | 2017 |
| Analysis of variation and ferroelectric layer thickness on negative capacitance nanowire field-effect transistor JK Lee, C Woo, J Kim, M Kang, J Jeon, H Shin Journal of Nanoscience and Nanotechnology 19 (10), 6710-6714, 2019 | 2 | 2019 |
| Improving BSIM Flicker Noise Model Y Seo, C Woo, M Lee, M Kang, J Jeon, H Shin 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 2421-2426, 2019 | 2 | 2019 |
| Characteristics according to parameters of line edge roughness in ultra-scaled gate-all-around nanowire FET D Son, K Ko, C Woo, M Kang, H Shin Journal of Nanoscience and Nanotechnology 17 (10), 7179-7182, 2017 | 2 | 2017 |
| Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM Y Seo, S Kim, K Ko, C Woo, M Kim, J Lee, M Kang, H Shin Solid-State Electronics 140, 69-73, 2018 | 1 | 2018 |
| Analysis on extension region in nanowire FET considering RC delay and electrical characteristics J Kim, C Woo, M Kang, H Shin 2017 Silicon Nanoelectronics Workshop (SNW), 43-44, 2017 | 1 | 2017 |
| Effect of Various Geometry Parameters on the Performance of Nanoplate Field Effect Transistor with Negative Capacitance C Woo, JK Lee, M Kang, J Jeon, H Shin Journal of Nanoscience and Nanotechnology 19 (10), 6736-6740, 2019 | | 2019 |
| Analysis and optimization of RC delay in vertical nanoplate FET C Woo, K Ko, J Kim, M Kim, M Kang, H Shin Solid-State Electronics 136, 81-85, 2017 | | 2017 |
| Investigation of Work Function Variation Induced by Metal Gate and Process Variation Effect in 3D Stacked Nanowire FET Devices K Ko, D Son, C Woo, M Kang, H Shin Journal of Nanoscience and Nanotechnology 17 (10), 7115-7120, 2017 | | 2017 |
| Analysis of RC delay for high performance in LFET and VFET C Woo, J Kim, M Kang, H Shin 2017 Silicon Nanoelectronics Workshop (SNW), 69-70, 2017 | | 2017 |
