Advait Madhavan
Advait Madhavan
Faculty Specialist
Verified email at nist.gov
Title
Cited by
Cited by
Year
Race logic: A hardware acceleration for dynamic programming algorithms
A Madhavan, T Sherwood, D Strukov
ACM SIGARCH Computer Architecture News 42 (3), 517-528, 2014
652014
A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit
B Chakrabarti, MA Lastras-Montaño, G Adam, M Prezioso, B Hoskins, ...
Scientific reports 7 (1), 1-10, 2017
632017
A configurable CMOS memory platform for 3D-integrated memristors
M Payvand, A Madhavan, MA Lastras-Montaño, A Ghofrani, J Rofeh, ...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1378-1381, 2015
172015
A 4-mm2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions
A Madhavan, T Sherwood, D Strukov
2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017
162017
Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration
J Rofeh, A Sodhi, M Payvand, MA Lastras-Montaño, A Ghofrani, ...
2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 957-962, 2015
152015
Energy-efficient stochastic computing with superparamagnetic tunnel junctions
MW Daniels, A Madhavan, P Talatchian, A Mizrahi, MD Stiles
Physical review applied 13 (3), 034016, 2020
122020
Boosted race trees for low energy classification
G Tzimpragos, A Madhavan, D Vasudevan, D Strukov, T Sherwood
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
92019
High-throughput pattern matching with CMOL FPGA circuits: Case for logic-in-memory computing
A Madhavan, T Sherwood, DB Strukov
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018
92018
Streaming batch eigenupdates for hardware neural networks
BD Hoskins, MW Daniels, S Huang, A Madhavan, GC Adam, N Zhitenev, ...
Frontiers in neuroscience 13, 793, 2019
72019
Race logic: abusing hardware race conditions to perform useful computation
A Madhavan, T Sherwood, D Strukov
IEEE Micro 35 (3), 48-57, 2015
62015
Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits
A Madhavan, DB Strukov
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
62012
A novel shape based batching and prediction approach for time series using HMMS and FISS
S Srivastava, S Bhardwaj, A Madhvan, JRP Gupta
2010 10th International Conference on Intelligent Systems Design and …, 2010
62010
Roadmap on emerging hardware and technology for machine learning
K Berggren, Q Xia, KK Likharev, DB Strukov, H Jiang, T Mikolajick, ...
Nanotechnology 32 (1), 012002, 2020
52020
Energy efficient computation with asynchronous races
A Madhavan, T Sherwood, D Strukov
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
52016
A computational temporal logic for superconducting accelerators
G Tzimpragos, D Vasudevan, N Tsiskaridze, G Michelogiannakis, ...
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
42020
Storing and retrieving wavefronts with resistive temporal memory
A Madhavan, MD Stiles
IEEE International Symposium on Circuits and Systems (ISCAS), 2019
42019
3D ReRAM arrays and crossbars: Fabrication, characterization and applications
GC Adam, B Chrakrabarti, H Nili, B Hoskins, MA Lastras-Montaño, ...
2017 Ieee 17th International Conference on Nanotechnology (Ieee-Nano), 844-849, 2017
42017
Correction: Corrigendum: A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit
B Chakrabarti, MA Lastras-Montaño, G Adam, M Prezioso, B Hoskins, ...
Scientific reports 7 (1), 1-1, 2017
32017
A novel shape based batching and prediction approach for sunspot data using HMMS and ANNs
S Bhardwaj, S Srivastava, JRP Gupta, A Madhvan
India International Conference on Power Electronics 2010 (IICPE2010), 1-5, 2011
32011
Temporal memory with magnetic racetracks
H Vakili, MN Sakib, S Ganguly, M Stan, MW Daniels, A Madhavan, ...
arXiv preprint arXiv:2005.10704, 2020
22020
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Articles 1–20