Follow
Rajul Bansal
Rajul Bansal
Scientist Fellow, CSIR-CEERI
Verified email at ceeri.res.in
Title
Cited by
Cited by
Year
Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design
R Bansal, A Karmakar
Microprocessors and Microsystems 51, 56-75, 2017
122017
High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform
AD Darji, R Bansal, SN Merchant, AN Chandorkar
Proceedings of the 2011 Conference on Design & Architectures for Signal …, 2011
42011
Closely-coupled lifting hardware for efficient DWT computation in an SoC
R Bansal, A Karmakar
Journal of Signal Processing Systems 92 (2), 225-237, 2020
32020
A lifting instruction for performing DWT in LEON3 processor based System-on-Chip
R Bansal, MK Jatav, A Karmakar
VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017
22017
PRESENT crypto-core as closely-coupled coprocessor for efficient embedded socs
R Bansal
2020 24th International Symposium on VLSI Design and Test (VDAT), 1-6, 2020
12020
Efficient closely-coupled integration of AES coprocessor with LEON3 processor
R Bansal, A Karmakar
International Symposium on VLSI Design and Test, 345-356, 2019
12019
The system can't perform the operation now. Try again later.
Articles 1–6