T. Ghani
T. Ghani
Intel Fellow
Verified email at intel.com
Title
Cited by
Cited by
Year
A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging
K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ...
2007 IEEE International Electron Devices Meeting, 247-250, 2007
13232007
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
T Ghani, M Armstrong, C Auth, M Bost, P Charvat, G Glass, T Hoffmann, ...
IEEE International Electron Devices Meeting 2003, 11.6. 1-11.6. 3, 2003
9082003
A 90-nm logic technology featuring strained-silicon
SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ...
IEEE Transactions on electron devices 51 (11), 1790-1797, 2004
8142004
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C Auth, C Allen, A Blattner, D Bergstrom, M Brazier, M Bost, M Buehler, ...
2012 symposium on VLSI technology (VLSIT), 131-132, 2012
7832012
A logic nanotechnology featuring strained-silicon
SE Thompson, M Armstrong, C Auth, S Cea, R Chau, G Glass, T Hoffman, ...
IEEE Electron Device Letters 25 (4), 191-193, 2004
6052004
A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2SRAM cell size
S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ...
2014 IEEE International Electron Devices Meeting, 3.7. 1-3.7. 3, 2014
5312014
Semiconductor transistor having a stressed channel
A Murthy, RS Chau, T Ghani, KR Mistry
US Patent 6,621,131, 2003
5232003
45nm high-k+ metal gate strain-enhanced transistors
C Auth, A Cappellani, JS Chun, A Dalis, A Davis, T Ghani, G Glass, ...
2008 Symposium on VLSI Technology, 128-129, 2008
4232008
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell
S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ...
Digest. International Electron Devices Meeting,, 61-64, 2002
4002002
The high-k solution
MT Bohr, RS Chau, T Ghani, K Mistry
IEEE spectrum 44 (10), 29-35, 2007
3762007
Method and apparatus for identifying an unknown work
EH Wold
US Patent 6,968,337, 2005
2772005
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande, ...
2009 IEEE international electron devices meeting (IEDM), 1-4, 2009
2622009
A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2SRAM cell size in a 291Mb array
S Natarajan, M Armstrong, M Bost, R Brain, M Brazier, CH Chang, ...
2008 IEEE International Electron Devices Meeting, 1-3, 2008
2622008
Semiconductor device having doped epitaxial region and its methods of fabrication
AS Murtthy, DB Aubertine, T Ghani, AJ Pethe
US Patent 8,598,003, 2013
2552013
Self-aligned contacts
MT Bohr, T Ghani, NM Rahhal-Orabi, SM Joshi, JM Steigerwald, JW Klaus, ...
US Patent 8,436,404, 2013
2492013
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
T Ghani, K Mistry, P Packan, S Thompson, M Stettler, S Tyagi, M Bohr
2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000
2472000
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
A Keshavarzi, S Ma, S Narendra, B Bloechel, K Mistry, T Ghani, S Borkar, ...
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
2442001
In search of" Forever," continued transistor scaling one new material at a time
SE Thompson, RS Chau, T Ghani, K Mistry, S Tyagi, MT Bohr
IEEE Transactions on semiconductor manufacturing 18 (1), 26-36, 2005
2342005
PMOS transistor strain optimization with raised junction regions
M Bohr, T Ghani, S Cea, K Mistry, C Auth, M Armstrong, K Zawadzki
US Patent App. 10/608,870, 2004
2252004
III-V layers for N-type and P-type MOS source-drain contacts
GA Glass, AS Murthy, T Ghani
US Patent 9,153,583, 2015
1942015
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